Lines Matching refs:smu
297 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
300 struct amdgpu_device *adev = smu->adev;
320 if ((smu->smc_fw_version < 0x004e3a00) ||
344 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
346 struct smu_table_context *table_context = &smu->smu_table;
349 struct smu_baco_context *smu_baco = &smu->smu_baco;
350 PPTable_t *pptable = smu->smu_table.driver_pptable;
357 smu->dc_controlled_by_gpio = true;
368 smu->od_enabled = false;
375 * smu->od_settings just points to the actual overdrive_table
377 smu->od_settings = &powerplay_table->overdrive_table;
379 smu->adev->pm.no_fan =
385 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
387 struct smu_table_context *table_context = &smu->smu_table;
404 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
406 struct smu_table_context *table_context = &smu->smu_table;
415 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
425 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
429 struct smu_table_context *smu_table = &smu->smu_table;
433 ret = smu_cmn_get_combo_pptable(smu);
443 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
445 struct smu_table_context *smu_table = &smu->smu_table;
446 struct amdgpu_device *adev = smu->adev;
449 if (amdgpu_sriov_vf(smu->adev))
452 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
458 ret = smu_v13_0_0_store_powerplay_table(smu);
467 ret = smu_v13_0_0_append_powerplay_table(smu);
472 ret = smu_v13_0_0_check_powerplay_table(smu);
479 static int smu_v13_0_0_tables_init(struct smu_context *smu)
481 struct smu_table_context *smu_table = &smu->smu_table;
537 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
539 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
551 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
555 ret = smu_v13_0_0_tables_init(smu);
559 ret = smu_v13_0_0_allocate_dpm_context(smu);
563 return smu_v13_0_init_smc_tables(smu);
566 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
568 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
569 struct smu_table_context *table_context = &smu->smu_table;
579 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
580 ret = smu_v13_0_set_single_dpm_table(smu,
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
595 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
596 ret = smu_v13_0_set_single_dpm_table(smu,
620 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
628 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
629 ret = smu_v13_0_set_single_dpm_table(smu,
636 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
644 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
645 ret = smu_v13_0_set_single_dpm_table(smu,
652 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
660 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
661 ret = smu_v13_0_set_single_dpm_table(smu,
668 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
676 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
677 ret = smu_v13_0_set_single_dpm_table(smu,
684 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
711 ret = smu_v13_0_set_single_dpm_table(smu,
718 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
727 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
732 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
739 static void smu_v13_0_0_dump_pptable(struct smu_context *smu)
741 struct smu_table_context *table_context = &smu->smu_table;
745 dev_info(smu->adev->dev, "Dumped PPTable:\n");
747 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
748 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
749 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
752 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
755 return smu_v13_0_system_features_control(smu, en);
771 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
775 struct smu_table_context *smu_table = &smu->smu_table;
780 ret = smu_cmn_get_metrics_table(smu,
899 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
905 smu->smu_dpm.dpm_context;
938 dev_err(smu->adev->dev, "Unsupported clock type!\n");
950 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
955 struct smu_table_context *table_context = &smu->smu_table;
965 ret = smu_v13_0_0_get_smu_metrics_data(smu,
971 ret = smu_v13_0_0_get_smu_metrics_data(smu,
977 ret = smu_v13_0_0_get_smu_metrics_data(smu,
983 ret = smu_v13_0_0_get_smu_metrics_data(smu,
989 ret = smu_v13_0_0_get_smu_metrics_data(smu,
995 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1001 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1008 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1015 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1029 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
1036 clk_id = smu_cmn_to_asic_specific_index(smu,
1074 return smu_v13_0_0_get_smu_metrics_data(smu,
1079 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1082 PPTable_t *pptable = smu->smu_table.driver_pptable;
1089 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1094 PPTable_t *pptable = smu->smu_table.driver_pptable;
1157 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1160 struct amdgpu_device *adev = smu->adev;
1168 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1173 ret = smu_cmn_update_table(smu,
1179 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1184 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1189 ret = smu_cmn_update_table(smu,
1195 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1200 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
1204 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1207 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1260 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1262 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1302 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1308 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1334 if (!smu_v13_0_0_is_od_feature_supported(smu,
1345 if (!smu_v13_0_0_is_od_feature_supported(smu,
1356 if (!smu_v13_0_0_is_od_feature_supported(smu,
1366 if (!smu_v13_0_0_is_od_feature_supported(smu,
1378 smu_v13_0_0_get_od_setting_limits(smu,
1385 smu_v13_0_0_get_od_setting_limits(smu,
1395 if (!smu_v13_0_0_is_od_feature_supported(smu,
1404 smu_v13_0_0_get_od_setting_limits(smu,
1413 if (!smu_v13_0_0_is_od_feature_supported(smu,
1422 smu_v13_0_0_get_od_setting_limits(smu,
1431 if (!smu_v13_0_0_is_od_feature_supported(smu,
1440 smu_v13_0_0_get_od_setting_limits(smu,
1449 if (!smu_v13_0_0_is_od_feature_supported(smu,
1458 smu_v13_0_0_get_od_setting_limits(smu,
1467 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1468 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1469 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1474 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1475 smu_v13_0_0_get_od_setting_limits(smu,
1479 smu_v13_0_0_get_od_setting_limits(smu,
1487 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1488 smu_v13_0_0_get_od_setting_limits(smu,
1492 smu_v13_0_0_get_od_setting_limits(smu,
1500 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1501 smu_v13_0_0_get_od_setting_limits(smu,
1518 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1520 struct smu_table_context *table_context = &smu->smu_table;
1525 struct amdgpu_device *adev = smu->adev;
1571 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1576 struct smu_table_context *table_context = &smu->smu_table;
1579 struct amdgpu_device *adev = smu->adev;
1587 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1600 smu_v13_0_0_get_od_setting_limits(smu,
1616 smu_v13_0_0_get_od_setting_limits(smu,
1648 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1661 smu_v13_0_0_get_od_setting_limits(smu,
1677 smu_v13_0_0_get_od_setting_limits(smu,
1709 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1714 smu_v13_0_0_get_od_setting_limits(smu,
1731 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1740 smu_v13_0_0_get_od_setting_limits(smu,
1751 smu_v13_0_0_get_od_setting_limits(smu,
1769 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1774 smu_v13_0_0_get_od_setting_limits(smu,
1791 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1796 smu_v13_0_0_get_od_setting_limits(smu,
1813 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1818 smu_v13_0_0_get_od_setting_limits(smu,
1835 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1840 smu_v13_0_0_get_od_setting_limits(smu,
1858 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1881 smu_v13_0_0_dump_od_table(smu, od_table);
1883 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1897 smu->user_dpm_profile.user_od = false;
1899 smu->user_dpm_profile.user_od = true;
1910 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1914 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1975 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1994 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
1997 struct smu_table_context *table_context = &smu->smu_table;
2000 PPTable_t *pptable = smu->smu_table.driver_pptable;
2002 if (amdgpu_sriov_vf(smu->adev))
2028 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2031 struct smu_table_context *smu_table = &smu->smu_table;
2038 ret = smu_cmn_get_metrics_table(smu,
2110 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2112 struct amdgpu_device *adev = smu->adev;
2114 if (smu_v13_0_0_is_od_feature_supported(smu,
2128 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2131 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2133 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2135 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2140 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2144 smu_v13_0_0_dump_od_table(smu, boot_od_table);
2154 if (!smu->adev->in_suspend) {
2158 smu->user_dpm_profile.user_od = false;
2159 } else if (smu->user_dpm_profile.user_od) {
2193 smu_v13_0_0_set_supported_od_feature_mask(smu);
2198 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2200 struct smu_table_context *table_context = &smu->smu_table;
2209 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2217 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2220 smu->smu_dpm.dpm_context;
2234 &smu->pstate_table;
2235 struct smu_table_context *table_context = &smu->smu_table;
2276 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2278 struct smu_table_context *smu_table = &smu->smu_table;
2281 struct amdgpu_device *adev = smu->adev;
2285 ret = smu_cmn_get_metrics_table(smu, NULL, false);
2296 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2304 ret = smu_v13_0_0_get_smu_metrics_data(smu,
2308 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2318 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2324 return smu_v13_0_0_get_smu_metrics_data(smu,
2329 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2331 struct smu_table_context *table_context = &smu->smu_table;
2342 return smu_cmn_send_smc_msg_with_param(smu,
2348 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2354 struct smu_table_context *table_context = &smu->smu_table;
2362 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2363 power_limit = smu->adev->pm.ac_power ?
2373 if (smu->od_enabled &&
2374 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2377 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2383 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2399 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2429 workload_type = smu_cmn_to_asic_specific_index(smu,
2437 result = smu_cmn_update_table(smu,
2443 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2448 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2480 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2490 smu->power_profile_mode = input[size];
2492 if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
2493 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2497 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2498 ret = smu_cmn_update_table(smu,
2504 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2531 ret = smu_cmn_update_table(smu,
2537 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2543 workload_type = smu_cmn_to_asic_specific_index(smu,
2545 smu->power_profile_mode);
2553 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
2554 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2555 ((smu->adev->pm.fw_version == 0x004e6601) ||
2556 (smu->adev->pm.fw_version >= 0x004e7300))) ||
2557 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2558 smu->adev->pm.fw_version >= 0x00504500)) {
2559 workload_type = smu_cmn_to_asic_specific_index(smu,
2567 return smu_cmn_send_smc_msg_with_param(smu,
2573 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2575 struct amdgpu_device *adev = smu->adev;
2584 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2599 struct smu_context *smu = adev->powerplay.pp_handle;
2600 struct smu_table_context *smu_table = &smu->smu_table;
2650 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2690 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2692 struct amdgpu_device *adev = smu->adev;
2732 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2734 struct amdgpu_device *adev = smu->adev;
2747 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2754 ret = smu_cmn_send_smc_msg_with_param(smu,
2758 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
2759 ret = smu_v13_0_disable_pmfw_state(smu);
2770 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2773 return smu_cmn_send_smc_msg_with_param(smu,
2779 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2783 struct amdgpu_device *adev = smu->adev;
2786 if ((smu->smc_fw_version >= supported_version) &&
2794 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2798 struct amdgpu_device *adev = smu->adev;
2803 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m);
2805 ret = smu_cmn_send_smc_msg_with_param(smu,
2811 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m);
2813 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2818 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2828 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2831 struct amdgpu_device *adev = smu->adev;
2834 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2841 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2843 struct amdgpu_device *adev = smu->adev;
2846 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2852 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
2854 struct amdgpu_device *adev = smu->adev;
2856 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2857 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2858 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2860 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2861 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
2862 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
2865 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
2871 ret = smu_cmn_send_smc_msg_with_param(smu,
2875 dev_err(smu->adev->dev,
2882 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
2888 ret = smu_cmn_send_smc_msg_with_param(smu,
2892 dev_err(smu->adev->dev,
2899 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
2901 struct amdgpu_device *adev = smu->adev;
2905 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
2911 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
2914 struct smu_table_context *smu_table = &smu->smu_table;
2915 struct amdgpu_device *adev = smu->adev;
2921 ret = smu_v13_0_0_check_ecc_table_support(smu);
2925 ret = smu_cmn_update_table(smu,
2952 static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
2954 struct amdgpu_device *adev = smu->adev;
2958 return smu->smc_fw_version >= 0x004e6300;
2960 return smu->smc_fw_version >= 0x00503300;
2966 static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
2970 PPTable_t *pptable = smu->smu_table.driver_pptable;
2973 struct smu_table_context *table_context = &smu->smu_table;
2982 if (smu->current_power_limit > msg_limit) {
2986 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
2988 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2992 return smu_v13_0_set_power_limit(smu, limit_type, limit);
2993 } else if (smu->od_enabled) {
2994 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
3001 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3003 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3007 smu->current_power_limit = limit;
3098 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3100 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3101 smu->message_map = smu_v13_0_0_message_map;
3102 smu->clock_map = smu_v13_0_0_clk_map;
3103 smu->feature_map = smu_v13_0_0_feature_mask_map;
3104 smu->table_map = smu_v13_0_0_table_map;
3105 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3106 smu->workload_map = smu_v13_0_0_workload_map;
3107 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3108 smu_v13_0_0_set_smu_mailbox_registers(smu);