Lines Matching refs:smu
224 static int vangogh_tables_init(struct smu_context *smu)
226 struct smu_table_context *smu_table = &smu->smu_table;
270 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
274 struct smu_table_context *smu_table = &smu->smu_table;
278 ret = smu_cmn_get_metrics_table(smu,
329 smu->cpu_core_num * sizeof(uint16_t));
339 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
343 struct smu_table_context *smu_table = &smu->smu_table;
347 ret = smu_cmn_get_metrics_table(smu,
402 smu->cpu_core_num * sizeof(uint16_t));
412 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
418 if (smu->smc_fw_if_version < 0x3)
419 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
421 ret = vangogh_get_smu_metrics_data(smu, member, value);
426 static int vangogh_allocate_dpm_context(struct smu_context *smu)
428 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
440 static int vangogh_init_smc_tables(struct smu_context *smu)
444 ret = vangogh_tables_init(smu);
448 ret = vangogh_allocate_dpm_context(smu);
454 smu->cpu_core_num = topology_num_cores_per_package();
456 smu->cpu_core_num = 4;
459 return smu_v11_0_init_smc_tables(smu);
462 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
468 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
472 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
480 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
485 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
489 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
497 static bool vangogh_is_dpm_running(struct smu_context *smu)
499 struct amdgpu_device *adev = smu->adev;
507 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
515 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
518 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
558 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
561 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
563 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
570 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
581 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
583 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
588 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
590 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
592 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
599 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
601 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
623 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
639 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
660 static int vangogh_print_clk_levels(struct smu_context *smu,
663 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
665 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
673 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
684 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
686 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
691 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
693 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
695 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
702 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
704 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
726 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
732 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
749 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
765 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
766 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
788 static int vangogh_common_print_clk_levels(struct smu_context *smu,
793 if (smu->smc_fw_if_version < 0x3)
794 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
796 ret = vangogh_print_clk_levels(smu, clk_type, buf);
801 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
809 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
855 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
881 if (!smu_cmn_feature_is_enabled(smu, feature_id))
887 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
900 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
904 clock_limit = smu->smu_table.boot_values.uclk;
907 clock_limit = smu->smu_table.boot_values.fclk;
911 clock_limit = smu->smu_table.boot_values.gfxclk;
914 clock_limit = smu->smu_table.boot_values.socclk;
917 clock_limit = smu->smu_table.boot_values.vclk;
920 clock_limit = smu->smu_table.boot_values.dclk;
936 ret = vangogh_get_profiling_clk_mask(smu,
949 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
954 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
959 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
964 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
969 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
982 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
987 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
992 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
997 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1002 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1015 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1029 workload_type = smu_cmn_to_asic_specific_index(smu,
1037 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1043 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1049 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1058 workload_type = smu_cmn_to_asic_specific_index(smu,
1062 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1067 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1071 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1076 smu->power_profile_mode = profile_mode;
1081 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1088 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1094 ret = smu_cmn_send_smc_msg_with_param(smu,
1100 ret = smu_cmn_send_smc_msg_with_param(smu,
1107 ret = smu_cmn_send_smc_msg_with_param(smu,
1113 ret = smu_cmn_send_smc_msg_with_param(smu,
1120 ret = smu_cmn_send_smc_msg_with_param(smu,
1126 ret = smu_cmn_send_smc_msg_with_param(smu,
1133 ret = smu_cmn_send_smc_msg_with_param(smu,
1138 ret = smu_cmn_send_smc_msg_with_param(smu,
1145 ret = smu_cmn_send_smc_msg_with_param(smu,
1150 ret = smu_cmn_send_smc_msg_with_param(smu,
1163 static int vangogh_force_clk_levels(struct smu_context *smu,
1175 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1179 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1183 ret = smu_cmn_send_smc_msg_with_param(smu,
1188 ret = smu_cmn_send_smc_msg_with_param(smu,
1195 ret = vangogh_get_dpm_clk_limited(smu,
1199 ret = vangogh_get_dpm_clk_limited(smu,
1203 ret = smu_cmn_send_smc_msg_with_param(smu,
1208 ret = smu_cmn_send_smc_msg_with_param(smu,
1215 ret = vangogh_get_dpm_clk_limited(smu,
1220 ret = vangogh_get_dpm_clk_limited(smu,
1226 ret = smu_cmn_send_smc_msg_with_param(smu,
1232 ret = smu_cmn_send_smc_msg_with_param(smu,
1240 ret = vangogh_get_dpm_clk_limited(smu,
1245 ret = vangogh_get_dpm_clk_limited(smu,
1250 ret = smu_cmn_send_smc_msg_with_param(smu,
1256 ret = smu_cmn_send_smc_msg_with_param(smu,
1270 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1285 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1290 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1298 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1316 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1321 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1326 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1335 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1341 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1345 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1349 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1353 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1357 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1361 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1365 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1369 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1376 static int vangogh_set_performance_level(struct smu_context *smu,
1383 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1384 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1388 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1389 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1392 ret = vangogh_force_dpm_limit_value(smu, true);
1397 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1398 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1400 ret = vangogh_force_dpm_limit_value(smu, false);
1405 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1406 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1408 ret = vangogh_unforce_dpm_levels(smu);
1413 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1414 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1416 ret = vangogh_get_profiling_clk_mask(smu, level,
1425 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1426 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1427 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1428 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1431 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1432 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1435 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1436 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1438 ret = vangogh_get_profiling_clk_mask(smu, level,
1447 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1450 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1451 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1453 ret = vangogh_set_peak_clock_by_device(smu);
1463 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1464 smu->gfx_actual_hard_min_freq, NULL);
1468 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1469 smu->gfx_actual_soft_max_freq, NULL);
1473 if (smu->adev->pm.fw_version >= 0x43f1b00) {
1474 for (i = 0; i < smu->cpu_core_num; i++) {
1475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1477 | smu->cpu_actual_soft_min_freq),
1482 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1484 | smu->cpu_actual_soft_max_freq),
1494 static int vangogh_read_sensor(struct smu_context *smu,
1505 ret = vangogh_common_get_smu_metrics_data(smu,
1511 ret = vangogh_common_get_smu_metrics_data(smu,
1517 ret = vangogh_common_get_smu_metrics_data(smu,
1523 ret = vangogh_common_get_smu_metrics_data(smu,
1529 ret = vangogh_common_get_smu_metrics_data(smu,
1535 ret = vangogh_common_get_smu_metrics_data(smu,
1542 ret = vangogh_common_get_smu_metrics_data(smu,
1549 ret = vangogh_common_get_smu_metrics_data(smu,
1555 ret = vangogh_common_get_smu_metrics_data(smu,
1561 ret = vangogh_common_get_smu_metrics_data(smu,
1564 *size = smu->cpu_core_num * sizeof(uint16_t);
1574 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1576 return smu_cmn_send_smc_msg_with_param(smu,
1581 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1583 return smu_cmn_send_smc_msg_with_param(smu,
1589 static int vangogh_set_watermarks_table(struct smu_context *smu,
1594 Watermarks_t *table = smu->smu_table.watermarks_table;
1632 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1635 /* pass data to smu controller */
1636 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1637 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1638 ret = smu_cmn_write_watermarks_table(smu);
1640 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1643 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1649 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1652 struct smu_table_context *smu_table = &smu->smu_table;
1658 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1706 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1709 struct smu_table_context *smu_table = &smu->smu_table;
1715 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1763 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1766 struct smu_table_context *smu_table = &smu->smu_table;
1772 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1834 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1838 struct smu_table_context *smu_table = &smu->smu_table;
1843 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1914 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1917 struct smu_table_context *smu_table = &smu->smu_table;
1923 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1978 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1985 smu_program = (smu->smc_fw_version >> 24) & 0xff;
1986 fw_version = smu->smc_fw_version & 0xffffff;
1989 ret = vangogh_get_gpu_metrics_v2_4(smu, table);
1991 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1994 if (smu->smc_fw_version >= 0x043F3E00) {
1995 if (smu->smc_fw_if_version < 0x3)
1996 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
1998 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2000 if (smu->smc_fw_if_version < 0x3)
2001 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2003 ret = vangogh_get_gpu_metrics(smu, table);
2010 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2014 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2017 dev_warn(smu->adev->dev,
2025 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2028 if (input[0] >= smu->cpu_core_num) {
2029 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2030 smu->cpu_core_num);
2032 smu->cpu_core_id_select = input[0];
2034 if (input[2] < smu->cpu_default_soft_min_freq) {
2035 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2036 input[2], smu->cpu_default_soft_min_freq);
2039 smu->cpu_actual_soft_min_freq = input[2];
2041 if (input[2] > smu->cpu_default_soft_max_freq) {
2042 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2043 input[2], smu->cpu_default_soft_max_freq);
2046 smu->cpu_actual_soft_max_freq = input[2];
2053 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2058 if (input[1] < smu->gfx_default_hard_min_freq) {
2059 dev_warn(smu->adev->dev,
2061 input[1], smu->gfx_default_hard_min_freq);
2064 smu->gfx_actual_hard_min_freq = input[1];
2066 if (input[1] > smu->gfx_default_soft_max_freq) {
2067 dev_warn(smu->adev->dev,
2069 input[1], smu->gfx_default_soft_max_freq);
2072 smu->gfx_actual_soft_max_freq = input[1];
2079 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2082 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2083 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2084 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2085 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2090 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2093 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2094 dev_err(smu->adev->dev,
2096 smu->gfx_actual_hard_min_freq,
2097 smu->gfx_actual_soft_max_freq);
2101 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2102 smu->gfx_actual_hard_min_freq, NULL);
2104 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2108 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2109 smu->gfx_actual_soft_max_freq, NULL);
2111 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2115 if (smu->adev->pm.fw_version < 0x43f1b00) {
2116 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2120 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2121 ((smu->cpu_core_id_select << 20)
2122 | smu->cpu_actual_soft_min_freq),
2125 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2129 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2130 ((smu->cpu_core_id_select << 20)
2131 | smu->cpu_actual_soft_max_freq),
2134 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2146 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2148 struct smu_table_context *smu_table = &smu->smu_table;
2150 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2153 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2155 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2157 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2158 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2159 smu->gfx_actual_hard_min_freq = 0;
2160 smu->gfx_actual_soft_max_freq = 0;
2162 smu->cpu_default_soft_min_freq = 1400;
2163 smu->cpu_default_soft_max_freq = 3500;
2164 smu->cpu_actual_soft_min_freq = 0;
2165 smu->cpu_actual_soft_max_freq = 0;
2170 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2172 DpmClocks_t *table = smu->smu_table.clocks_table;
2196 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2198 struct amdgpu_device *adev = smu->adev;
2202 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2208 static int vangogh_post_smu_init(struct smu_context *smu)
2210 struct amdgpu_device *adev = smu->adev;
2220 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2222 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2250 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2254 static int vangogh_mode_reset(struct smu_context *smu, int type)
2258 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2263 mutex_lock(&smu->message_lock);
2265 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2267 mutex_unlock(&smu->message_lock);
2274 static int vangogh_mode2_reset(struct smu_context *smu)
2276 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2282 * @smu: amdgpu_device pointer
2292 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2294 struct amdgpu_device *adev = smu->adev;
2304 static int vangogh_get_power_limit(struct smu_context *smu,
2311 smu->smu_power.power_context;
2315 if (smu->adev->pm.fw_version < 0x43f1e00)
2318 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2320 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2333 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2335 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2346 static int vangogh_get_ppt_limit(struct smu_context *smu,
2352 smu->smu_power.power_context;
2376 static int vangogh_set_power_limit(struct smu_context *smu,
2381 smu->smu_power.power_context;
2384 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2385 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2391 ret = smu_cmn_send_smc_msg_with_param(smu,
2398 smu->current_power_limit = ppt_limit;
2403 dev_err(smu->adev->dev,
2409 ret = smu_cmn_send_smc_msg_with_param(smu,
2428 * @smu: amdgpu_device pointer
2436 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2440 struct amdgpu_device *adev = smu->adev;
2445 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2457 * @smu: amdgpu_device pointer
2464 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2466 struct amdgpu_device *adev = smu->adev;
2476 * @smu: amdgpu_device pointer
2483 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2486 struct amdgpu_device *adev = smu->adev;
2491 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2545 void vangogh_set_ppt_funcs(struct smu_context *smu)
2547 smu->ppt_funcs = &vangogh_ppt_funcs;
2548 smu->message_map = vangogh_message_map;
2549 smu->feature_map = vangogh_feature_mask_map;
2550 smu->table_map = vangogh_table_map;
2551 smu->workload_map = vangogh_workload_map;
2552 smu->is_apu = true;
2553 smu_v11_0_set_smu_mailbox_registers(smu);