Lines Matching defs:hwmgr
96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
102 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
179 if (!hwmgr->avfs_supported)
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
208 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
211 result = smu7_upload_smu_firmware_image(hwmgr);
216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
218 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
226 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
230 smu7_send_msg_to_smc_offset(hwmgr);
235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
237 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
243 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
246 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
250 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
267 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
271 result = smu7_upload_smu_firmware_image(hwmgr);
276 smu7_program_jump_on_start(hwmgr);
278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
281 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
286 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
298 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
299 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
300 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
304 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
306 result = polaris10_start_smu_in_protection_mode(hwmgr);
311 polaris10_avfs_event_mgr(hwmgr);
315 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
318 result = smu7_request_smu_load_fw(hwmgr);
323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
343 hwmgr->smu_backend = smu_data;
345 if (smu7_init(hwmgr)) {
353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
427 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
429 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
434 (struct phm_ppt_v1_information *)(hwmgr->pptable);
437 &hwmgr->thermal_controller.advanceFanControlParameters;
475 static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
477 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
480 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
482 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
484 if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
490 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
492 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
503 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
506 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
508 (struct phm_ppt_v1_information *)(hwmgr->pptable);
521 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
523 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
527 if (smu7_read_smc_sram_dword(hwmgr,
545 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
548 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
557 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
559 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
561 /* TO DO move to hwmgr */
562 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
563 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
564 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
565 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
568 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
572 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
575 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
584 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
586 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
588 (struct phm_ppt_v1_information *)(hwmgr->pptable);
604 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
606 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
609 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
611 if (smu7_read_smc_sram_dword(hwmgr,
619 if (polaris10_populate_svi_load_line(hwmgr))
624 if (polaris10_populate_tdc_limit(hwmgr))
628 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
634 if (0 != polaris10_populate_temperature_scaler(hwmgr))
639 if (polaris10_populate_fuzzy_fan(hwmgr))
644 if (polaris10_populate_gnb_lpml(hwmgr))
649 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
654 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
664 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
667 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
691 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
695 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
716 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
720 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
741 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
746 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
748 (struct phm_ppt_v1_information *)(hwmgr->pptable);
767 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
770 polaris10_populate_smc_vddc_table(hwmgr, table);
771 polaris10_populate_smc_vddci_table(hwmgr, table);
772 polaris10_populate_smc_mvdd_table(hwmgr, table);
773 polaris10_populate_cac_table(hwmgr, table);
778 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
781 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
783 (struct phm_ppt_v1_information *)(hwmgr->pptable);
784 struct amdgpu_device *adev = hwmgr->adev;
793 if ((hwmgr->chip_id == CHIP_POLARIS12) ||
809 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
812 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
815 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
818 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
819 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
839 /* To Do move to hwmgr */
847 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
850 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
855 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
857 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
890 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
893 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
920 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
955 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
961 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
963 (struct phm_ppt_v1_information *)(hwmgr->pptable);
967 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
969 if (hwmgr->od_enabled)
975 result = polaris10_get_dependency_volt_by_clk(hwmgr,
993 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
995 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
997 hwmgr->display_config->min_core_set_clock_in_sr);
1026 static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
1028 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1032 if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
1036 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1038 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1039 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1042 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1057 struct amdgpu_device *adev = hwmgr->adev;
1063 polaris10_get_vddc_shared_railinfo(hwmgr);
1065 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1069 result = polaris10_populate_single_graphic_level(hwmgr,
1079 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1083 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1089 smum_send_msg_to_smc_with_parameter(hwmgr,
1146 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1153 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1156 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1158 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1164 if (hwmgr->od_enabled)
1170 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1188 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1189 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1193 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1208 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1210 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1211 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1227 result = polaris10_populate_single_memory_level(hwmgr,
1246 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1252 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1255 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1257 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1277 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1282 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1284 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1293 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1302 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1328 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339 polaris10_populate_mvdd_value(hwmgr,
1343 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1365 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1372 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1375 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1401 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1415 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1422 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1425 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1450 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1464 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1473 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1478 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1479 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1480 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1490 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1492 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1493 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1500 result = polaris10_populate_memory_timing_parameters(hwmgr,
1505 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1512 hwmgr,
1520 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1527 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1530 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1555 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1562 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1577 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1581 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1617 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1619 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1620 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1622 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1650 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1652 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1653 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1655 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1666 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
1674 if (hwmgr->chip_id == CHIP_POLARIS10) {
1697 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1704 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1706 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1711 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1714 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1715 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1749 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1758 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1769 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1771 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1772 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1773 struct amdgpu_device *adev = hwmgr->adev;
1783 (struct phm_ppt_v1_information *)hwmgr->pptable;
1788 if (!hwmgr->avfs_supported)
1793 hwmgr->avfs_supported = 0;
1797 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1801 ((hwmgr->chip_id == CHIP_POLARIS12) && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) ||
1819 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
1868 result = smu7_read_smc_sram_dword(hwmgr,
1872 smu7_copy_bytes_to_smc(hwmgr,
1878 result = smu7_read_smc_sram_dword(hwmgr,
1881 smu7_copy_bytes_to_smc(hwmgr,
1896 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1898 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1900 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1913 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1916 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1917 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1920 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1927 polaris10_initialize_power_tune_defaults(hwmgr);
1930 polaris10_populate_smc_voltage_tables(hwmgr, table);
1933 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1937 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1945 result = polaris10_populate_ulv_state(hwmgr, table);
1948 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1952 result = polaris10_populate_smc_link_level(hwmgr, table);
1956 result = polaris10_populate_all_graphic_levels(hwmgr);
1960 result = polaris10_populate_all_memory_levels(hwmgr);
1964 result = polaris10_populate_smc_acpi_level(hwmgr, table);
1968 result = polaris10_populate_smc_vce_level(hwmgr, table);
1972 result = polaris10_populate_smc_samu_level(hwmgr, table);
1980 result = polaris10_program_memory_timing_parameters(hwmgr);
1984 result = polaris10_populate_smc_uvd_level(hwmgr, table);
1988 result = polaris10_populate_smc_boot_level(hwmgr, table);
1992 result = polaris10_populate_smc_initailial_state(hwmgr);
1996 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2000 polaris10_populate_zero_rpm_parameters(hwmgr);
2002 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2004 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2010 result = polaris10_populate_avfs_parameters(hwmgr);
2034 result = polaris10_populate_vr_config(hwmgr, table);
2041 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2047 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2051 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2054 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2056 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2057 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2061 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2066 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2068 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2078 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2083 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2084 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2094 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
2118 result = smu7_copy_bytes_to_smc(hwmgr,
2127 result = polaris10_populate_pm_fuses(hwmgr);
2134 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2136 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2140 return polaris10_program_memory_timing_parameters(hwmgr);
2145 static int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2147 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2149 if (!hwmgr->avfs_supported)
2152 smum_send_msg_to_smc_with_parameter(hwmgr,
2156 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2162 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2167 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2169 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2178 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2179 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2185 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2190 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2194 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2200 if (hwmgr->thermal_controller.use_hw_fan_control)
2203 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2208 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2209 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2210 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2211 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2213 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2214 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2215 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2216 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2221 fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2223 fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2225 fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2233 fan_table.HystDown = cpu_to_be16(hwmgr->
2242 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2244 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2251 hwmgr->device, CGS_IND_REG__SMC,
2254 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2258 if (!res && hwmgr->thermal_controller.
2260 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2262 hwmgr->thermal_controller.
2266 if (!res && hwmgr->thermal_controller.
2268 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2270 hwmgr->thermal_controller.
2275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2281 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2283 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2286 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2296 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2300 cgs_write_ind_register(hwmgr->device,
2303 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2305 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2307 smum_send_msg_to_smc_with_parameter(hwmgr,
2314 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2316 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2319 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2321 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2332 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2336 cgs_write_ind_register(hwmgr->device,
2339 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2340 smum_send_msg_to_smc_with_parameter(hwmgr,
2347 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2349 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2351 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2364 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2368 polaris10_update_uvd_smc_table(hwmgr);
2371 polaris10_update_vce_smc_table(hwmgr);
2374 polaris10_update_bif_smc_table(hwmgr);
2382 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2384 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2385 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2390 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2399 hwmgr,
2410 result = polaris10_program_mem_timing_parameters(hwmgr);
2492 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2494 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2495 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2500 result = smu7_read_smc_sram_dword(hwmgr,
2510 result = smu7_read_smc_sram_dword(hwmgr,
2522 result = smu7_read_smc_sram_dword(hwmgr,
2530 result = smu7_read_smc_sram_dword(hwmgr,
2540 result = smu7_read_smc_sram_dword(hwmgr,
2550 result = smu7_read_smc_sram_dword(hwmgr,
2556 hwmgr->microcode_version_info.SMC = tmp;
2563 static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2565 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2568 static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2570 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2572 uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
2576 return atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
2579 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2581 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2586 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2589 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2591 (hwmgr->smu_backend);
2612 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2621 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2623 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2635 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2638 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2642 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2647 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2656 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2658 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2670 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2673 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2677 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);