pm/legacy-dpm/legacy_dpm.c

127 	if (rps == adev->pm.dpm.current_ps)
129 	if (rps == adev->pm.dpm.requested_ps)
131 	if (rps == adev->pm.dpm.boot_ps)
143 	for (i = 0; i < adev->pm.dpm.num_ps; i++)
144 		amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
172 	adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
173 	adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
174 	adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
242 			adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
243 			adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
244 			adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
245 			adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
246 			adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
247 			adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
248 			adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
250 				adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
252 				adev->pm.dpm.fan.t_max = 10900;
253 			adev->pm.dpm.fan.cycle_delay = 100000;
255 				adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode;
256 				adev->pm.dpm.fan.default_max_fan_pwm =
258 				adev->pm.dpm.fan.default_fan_output_sensitivity = 4836;
259 				adev->pm.dpm.fan.fan_output_sensitivity =
262 			adev->pm.dpm.fan.ucode_fan_control = true;
273 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
282 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
291 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
300 			ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
311 				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
314 				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
317 				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
319 				adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
330 			adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
334 			if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
339 				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
341 				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
343 				adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
348 			adev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
356 		adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
357 		adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
358 		adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit;
359 		adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
360 		if (adev->pm.dpm.tdp_od_limit)
361 			adev->pm.dpm.power_control = true;
363 			adev->pm.dpm.power_control = false;
364 		adev->pm.dpm.tdp_adjustment = 0;
365 		adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
366 		adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
367 		adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
375 			adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
376 			if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries)
380 				if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
381 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
383 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
385 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
388 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
390 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
396 			adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
427 			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
429 			if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
431 			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
439 				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
441 				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
443 				adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
448 			adev->pm.dpm.num_of_vce_states =
451 			for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
455 				adev->pm.dpm.vce_states[i].evclk =
457 				adev->pm.dpm.vce_states[i].ecclk =
459 				adev->pm.dpm.vce_states[i].clk_idx =
461 				adev->pm.dpm.vce_states[i].pstate =
480 			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
482 			if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
484 			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
491 				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
493 				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
495 				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
510 			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
512 			if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)
514 			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
518 				adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk =
520 				adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
531 			adev->pm.dpm.dyn_state.ppm_table =
533 			if (!adev->pm.dpm.dyn_state.ppm_table)
535 			adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
536 			adev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
538 			adev->pm.dpm.dyn_state.ppm_table->platform_tdp =
540 			adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
542 			adev->pm.dpm.dyn_state.ppm_table->platform_tdc =
544 			adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
546 			adev->pm.dpm.dyn_state.ppm_table->apu_tdp =
548 			adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
550 			adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
552 			adev->pm.dpm.dyn_state.ppm_table->tj_max =
564 			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
566 			if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)
568 			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
572 				adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk =
574 				adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
585 			adev->pm.dpm.dyn_state.cac_tdp_table =
587 			if (!adev->pm.dpm.dyn_state.cac_tdp_table)
593 				adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
600 				adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
603 			adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
604 			adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
606 			adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
607 			adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
609 			adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
611 			adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
613 			adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
622 					&adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk,
634 	struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state;
694 			adev->pm.no_fan = true;
695 		adev->pm.fan_pulses_per_revolution =
697 		if (adev->pm.fan_pulses_per_revolution) {
698 			adev->pm.fan_min_rpm = controller->ucFanMinRPM;
699 			adev->pm.fan_max_rpm = controller->ucFanMaxRPM;
705 			adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
710 			adev->pm.int_thermal_type = THERMAL_TYPE_RV770;
715 			adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
720 			adev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
725 			adev->pm.int_thermal_type = THERMAL_TYPE_NI;
730 			adev->pm.int_thermal_type = THERMAL_TYPE_SI;
735 			adev->pm.int_thermal_type = THERMAL_TYPE_CI;
740 			adev->pm.int_thermal_type = THERMAL_TYPE_KV;
745 			adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
751 			adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
757 			adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
764 			adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
766 			adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus);
767 			if (adev->pm.i2c_bus) {
772 				i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info);
788 	if (idx < adev->pm.dpm.num_of_vce_states)
789 		return &adev->pm.dpm.vce_states[idx];
800 	bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
820 	for (i = 0; i < adev->pm.dpm.num_ps; i++) {
821 		ps = &adev->pm.dpm.ps[i];
854 			if (adev->pm.dpm.uvd_ps)
855 				return adev->pm.dpm.uvd_ps;
875 			return adev->pm.dpm.boot_ps;
904 		if (adev->pm.dpm.uvd_ps) {
905 			return adev->pm.dpm.uvd_ps;
937 	if (!adev->pm.dpm_enabled)
940 	if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
942 		if ((!adev->pm.dpm.thermal_active) &&
943 		    (!adev->pm.dpm.uvd_active))
944 			adev->pm.dpm.state = adev->pm.dpm.user_state;
946 	dpm_state = adev->pm.dpm.state;
950 		adev->pm.dpm.requested_ps = ps;
956 		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
958 		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
962 	ps->vce_active = adev->pm.dpm.vce_active;
971 		if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
983 	adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
984 	adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
987 		if (adev->pm.dpm.thermal_active) {
988 			enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
992 			adev->pm.dpm.forced_level = level;
995 			pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level);
1015 			     pm.dpm.thermal.work);
1021 	if (!adev->pm.dpm_enabled)
1028 		if (temp < adev->pm.dpm.thermal.min_temp)
1030 			dpm_state = adev->pm.dpm.user_state;
1032 		if (adev->pm.dpm.thermal.high_to_low)
1034 			dpm_state = adev->pm.dpm.user_state;
1038 		adev->pm.dpm.thermal_active = true;
1040 		adev->pm.dpm.thermal_active = false;
1042 	adev->pm.dpm.state = dpm_state;