Lines Matching defs:ULONG
44 #ifndef ULONG
45 typedef unsigned long ULONG;
262 ULONG ulPSPDirTableOffset;
427 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
429 ULONG ulClockFreq:24;
431 ULONG ulClockFreq:24;
432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
433 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
440 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
449 ULONG ulClock; //When return, [23:0] return real clock
478 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
497 ULONG ulClockParams; //ULONG access for BE
517 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
518 ULONG ulClock:24; //Input= target clock, output = actual clock
520 ULONG ulClock:24; //Input= target clock, output = actual clock
521 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
530 ULONG ulClockParams; //ULONG access for BE
547 ULONG ulReserved[2];
572 ULONG ulReserved[5];
605 ULONG ulClock;
632 ULONG ulReserved;
647 ULONG ulReserved[2];
655 ULONG ulMemoryClock;
656 ULONG ulReserved;
666 ULONG ulReserved;
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
734 ULONG ulClkFreqIn10Khz:24;
735 ULONG ucClkFlag:8;
747 ULONG ulReserved[8];
775 ULONG ulReserved[4];
804 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1087 ULONG ulPixelClock; // Pixel Clock in 10Khz
1099 ULONG ulSymClock; // Symbol Clock in 10Khz
1113 ULONG ulReserved[2];
1121 ULONG ulReserved[2];
1569 ULONG ulSymClock; // Symbol Clock in 10Khz
1574 ULONG ulReserved;
1647 ULONG ulReserved[2];
1933 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1948 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1950 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1953 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1955 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1964 ULONG ulDispEngClkFreq; // dispclk frequency
1981 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
2017 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2032 ULONG ulReserved;
2054 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
2065 ULONG ulReserved[2];
2076 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2106 ULONG ulReserved[2];
2155 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2376 ULONG ulTargetMemoryClock; //In 10Khz unit
2673 ULONG ulReserved;
2679 ULONG ulVotlageGpioState;
2680 ULONG ulVoltageGPioMask;
2688 ULONG ulReseved;
2712 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2734 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2735 ULONG ulReserved[3];
2741 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
2742 ULONG ulReserved[4];
2751 ULONG ulDfsPllOutputFreq:24;
2752 ULONG ucDfsDivider:8;
2757 ULONG ulDfsOutputFreq;
2842 ULONG ulSignature; // HW info table signature string "$ATI"
2856 ULONG ulSignature; // MM info table signature sting "$MMT"
2951 ULONG ulFirmwareRevision;
2952 ULONG ulDefaultEngineClock; //In 10Khz unit
2953 ULONG ulDefaultMemoryClock; //In 10Khz unit
2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2959 ULONG ulASICMaxEngineClock; //In 10Khz unit
2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2963 ULONG aulReservedForBIOS[3]; //Don't use them
2985 ULONG ulFirmwareRevision;
2986 ULONG ulDefaultEngineClock; //In 10Khz unit
2987 ULONG ulDefaultMemoryClock; //In 10Khz unit
2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2993 ULONG ulASICMaxEngineClock; //In 10Khz unit
2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2998 ULONG aulReservedForBIOS[2]; //Don't use them
2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3021 ULONG ulFirmwareRevision;
3022 ULONG ulDefaultEngineClock; //In 10Khz unit
3023 ULONG ulDefaultMemoryClock; //In 10Khz unit
3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3029 ULONG ulASICMaxEngineClock; //In 10Khz unit
3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3034 ULONG aulReservedForBIOS; //Don't use them
3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3058 ULONG ulFirmwareRevision;
3059 ULONG ulDefaultEngineClock; //In 10Khz unit
3060 ULONG ulDefaultMemoryClock; //In 10Khz unit
3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3066 ULONG ulASICMaxEngineClock; //In 10Khz unit
3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3097 ULONG ulFirmwareRevision;
3098 ULONG ulDefaultEngineClock; //In 10Khz unit
3099 ULONG ulDefaultMemoryClock; //In 10Khz unit
3100 ULONG ulReserved1;
3101 ULONG ulReserved2;
3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3105 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3112 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3147 ULONG ulFirmwareRevision;
3148 ULONG ulDefaultEngineClock; //In 10Khz unit
3149 ULONG ulDefaultMemoryClock; //In 10Khz unit
3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3152 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3153 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3155 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
3156 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
3162 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3166 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
3167 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
3182 ULONG ulReserved10[3]; // New added comparing to previous version
3203 ULONG ulBootUpEngineClock; //in 10kHz unit
3204 ULONG ulBootUpMemoryClock; //in 10kHz unit
3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3212 ULONG ulReserved[2];
3275 ULONG ulBootUpEngineClock; //in 10kHz unit
3276 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3277 ULONG ulBootUpUMAClock; //in 10kHz unit
3278 ULONG ulBootUpSidePortClock; //in 10kHz unit
3279 ULONG ulMinSidePortClock; //in 10kHz unit
3280 ULONG ulReserved2[6]; //must be 0x0 for the reserved
3281 ULONG ulSystemConfig; //see explanation below
3282 ULONG ulBootUpReqDisplayVector;
3283 ULONG ulOtherDisplayMisc;
3284 ULONG ulDDISlot1Config;
3285 ULONG ulDDISlot2Config;
3290 ULONG ulDockingPinCFGInfo;
3291 ULONG ulCPUCapInfo;
3296 ULONG ulHTLinkFreq; //in 10Khz
3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3311 ULONG ulReserved3[96]; //must be 0x0
3449 ULONG ulBootUpEngineClock; //in 10kHz unit
3450 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
3451 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3452 ULONG ulBootUpUMAClock; //in 10kHz unit
3453 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3454 ULONG ulBootUpReqDisplayVector;
3455 ULONG ulOtherDisplayMisc;
3456 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3457 ULONG ulSystemConfig; //TBD
3458 ULONG ulCPUCapInfo; //TBD
3464 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3465 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3466 ULONG ulDDISlot2Config;
3467 ULONG ulDDISlot3Config;
3468 ULONG ulDDISlot4Config;
3469 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3473 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3474 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3475 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3476 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3477 ULONG ulReserved6[61]; //must be 0x0
3488 ULONG ulMCUcodeRomStartAddr;
3489 ULONG ulMCUcodeLength;
3490 ULONG ulSMCUcodeRomStartAddr;
3491 ULONG ulSMCUcodeLength;
3492 ULONG ulRLCVUcodeRomStartAddr;
3493 ULONG ulRLCVUcodeLength;
3494 ULONG ulTOCUcodeStartAddr;
3495 ULONG ulTOCUcodeLength;
3496 ULONG ulSMCPatchTableStartAddr;
3497 ULONG ulSmcPatchTableLength;
3498 ULONG ulSystemFlag;
3998 ULONG ulReserved0;
4036 ULONG ulReserved[2];
4333 ULONG ulStartAddrUsedByFirmware;
4347 ULONG ulStartAddrUsedByFirmware;
4726 ULONG ulACPIDeviceEnum; //Reserved for now
4826 ULONG ulStrengthControl; // DVOA strength control for CF
5128 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
5163 ULONG ulGpioMaskVal; // GPIO Mask value
5173 ULONG ulMaxVoltageLevel;
5190 ULONG ulReserved;
5205 ULONG ulDPMSclk; // DPM state SCLK
5278 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5279 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5288 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5289 ULONG ulEfuseMin; // Min
5296 ULONG ulEvvDerateTdp;
5297 ULONG ulEvvDerateTdc;
5298 ULONG ulBoardCoreTemp;
5299 ULONG ulMaxVddc;
5300 ULONG ulMinVddc;
5301 ULONG ulLoadLineSlop;
5302 ULONG ulLeakageTemp;
5303 ULONG ulLeakageVoltage;
5312 ULONG ulLkgEncodeLn_MaxDivMin;
5313 ULONG ulLkgEncodeMax;
5314 ULONG ulLkgEncodeMin;
5315 ULONG ulEfuseLogisticAlpha;
5338 ULONG ulEvvLkgFactor;
5339 ULONG ulBoardCoreTemp;
5340 ULONG ulMaxVddc;
5341 ULONG ulMinVddc;
5342 ULONG ulLoadLineSlop;
5343 ULONG ulLeakageTemp;
5344 ULONG ulLeakageVoltage;
5353 ULONG ulLkgEncodeLn_MaxDivMin;
5354 ULONG ulLkgEncodeMax;
5355 ULONG ulLkgEncodeMin;
5356 ULONG ulEfuseLogisticAlpha;
5365 ULONG ulTdpDerateDPM0;
5366 ULONG ulTdpDerateDPM1;
5367 ULONG ulTdpDerateDPM2;
5368 ULONG ulTdpDerateDPM3;
5369 ULONG ulTdpDerateDPM4;
5370 ULONG ulTdpDerateDPM5;
5371 ULONG ulTdpDerateDPM6;
5372 ULONG ulTdpDerateDPM7;
5380 ULONG ulEvvLkgFactor;
5381 ULONG ulBoardCoreTemp;
5382 ULONG ulMaxVddc;
5383 ULONG ulMinVddc;
5384 ULONG ulLoadLineSlop;
5385 ULONG ulLeakageTemp;
5386 ULONG ulLeakageVoltage;
5395 ULONG ulLkgEncodeLn_MaxDivMin;
5396 ULONG ulLkgEncodeMax;
5397 ULONG ulLkgEncodeMin;
5398 ULONG ulEfuseLogisticAlpha;
5411 ULONG ulTdpDerateDPM0;
5412 ULONG ulTdpDerateDPM1;
5413 ULONG ulTdpDerateDPM2;
5414 ULONG ulTdpDerateDPM3;
5415 ULONG ulTdpDerateDPM4;
5416 ULONG ulTdpDerateDPM5;
5417 ULONG ulTdpDerateDPM6;
5418 ULONG ulTdpDerateDPM7;
5420 ULONG ulRoAlpha;
5421 ULONG ulRoBeta;
5422 ULONG ulRoGamma;
5423 ULONG ulRoEpsilon;
5424 ULONG ulATermRo;
5425 ULONG ulBTermRo;
5426 ULONG ulCTermRo;
5427 ULONG ulSclkMargin;
5428 ULONG ulFmaxPercent;
5429 ULONG ulCRPercent;
5430 ULONG ulSFmaxPercent;
5431 ULONG ulSCRPercent;
5432 ULONG ulSDCMargine;
5439 ULONG ulEvvLkgFactor;
5440 ULONG ulBoardCoreTemp;
5441 ULONG ulMaxVddc;
5442 ULONG ulMinVddc;
5443 ULONG ulLoadLineSlop;
5444 ULONG ulLeakageTemp;
5445 ULONG ulLeakageVoltage;
5454 ULONG ulLkgEncodeLn_MaxDivMin;
5455 ULONG ulLkgEncodeMax;
5456 ULONG ulLkgEncodeMin;
5457 ULONG ulEfuseLogisticAlpha;
5466 ULONG ulTdpDerateDPM0;
5467 ULONG ulTdpDerateDPM1;
5468 ULONG ulTdpDerateDPM2;
5469 ULONG ulTdpDerateDPM3;
5470 ULONG ulTdpDerateDPM4;
5471 ULONG ulTdpDerateDPM5;
5472 ULONG ulTdpDerateDPM6;
5473 ULONG ulTdpDerateDPM7;
5475 ULONG ulEvvDefaultVddc;
5476 ULONG ulEvvNoCalcVddc;
5479 ULONG ulSM_A0;
5480 ULONG ulSM_A1;
5481 ULONG ulSM_A2;
5482 ULONG ulSM_A3;
5483 ULONG ulSM_A4;
5484 ULONG ulSM_A5;
5485 ULONG ulSM_A6;
5486 ULONG ulSM_A7;
5495 ULONG ulMargin_RO_a;
5496 ULONG ulMargin_RO_b;
5497 ULONG ulMargin_RO_c;
5498 ULONG ulMargin_fixed;
5499 ULONG ulMargin_Fmax_mean;
5500 ULONG ulMargin_plat_mean;
5501 ULONG ulMargin_Fmax_sigma;
5502 ULONG ulMargin_plat_sigma;
5503 ULONG ulMargin_DC_sigma;
5504 ULONG ulReserved[8]; // Reserved for future ASIC
5511 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv
5512 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv
5516 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
5517 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5518 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5520 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
5521 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>
5522 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
5523 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
5524 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
5525 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
5526 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
5527 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
5528 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
5529 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
5530 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>
5539 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
5540 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
5541 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
5542 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
5543 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>
5544 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
5545 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
5546 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
5547 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
5548 ULONG ulReserved[12];
5555 ULONG ulMaxVddc;
5556 ULONG ulMinVddc;
5560 ULONG ulLkgEncodeLn_MaxDivMin;
5561 ULONG ulLkgEncodeMax;
5562 ULONG ulLkgEncodeMin;
5564 ULONG ulEvvDefaultVddc;
5565 ULONG ulEvvNoCalcVddc;
5566 ULONG ulSpeed_Model;
5567 ULONG ulSM_A0;
5568 ULONG ulSM_A1;
5569 ULONG ulSM_A2;
5570 ULONG ulSM_A3;
5571 ULONG ulSM_A4;
5572 ULONG ulSM_A5;
5573 ULONG ulSM_A6;
5574 ULONG ulSM_A7;
5583 ULONG ulMargin_RO_a;
5584 ULONG ulMargin_RO_b;
5585 ULONG ulMargin_RO_c;
5586 ULONG ulMargin_fixed;
5587 ULONG ulMargin_Fmax_mean;
5588 ULONG ulMargin_plat_mean;
5589 ULONG ulMargin_Fmax_sigma;
5590 ULONG ulMargin_plat_sigma;
5591 ULONG ulMargin_DC_sigma;
5592 ULONG ulLoadLineSlop;
5593 ULONG ulaTDClimitPerDPM[8];
5594 ULONG ulaNoCalcVddcPerDPM[8];
5595 ULONG ulAVFS_meanNsigma_Acontant0;
5596 ULONG ulAVFS_meanNsigma_Acontant1;
5597 ULONG ulAVFS_meanNsigma_Acontant2;
5601 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5602 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5603 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5604 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5605 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5606 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5607 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5609 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5610 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5612 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5625 ULONG ulMaxSclkFreq;
5712 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
5713 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5720 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5725 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5737 ULONG ulBootUpEngineClock;
5738 ULONG ulDentistVCOFreq;
5739 ULONG ulBootUpUMAClock;
5741 ULONG ulBootUpReqDisplayVector;
5742 ULONG ulOtherDisplayMisc;
5743 ULONG ulGPUCapInfo;
5744 ULONG ulSB_MMIO_Base_Addr;
5748 ULONG ulMinEngineClock;
5749 ULONG ulSystemConfig;
5750 ULONG ulCPUCapInfo;
5758 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5759 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5760 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5762 ULONG ulGMCRestoreResetTime;
5763 ULONG ulMinimumNClk;
5764 ULONG ulIdleNClk;
5765 ULONG ulDDR_DLL_PowerUpTime;
5766 ULONG ulDDR_PLL_PowerUpTime;
5775 ULONG SclkDpmBoostMargin;
5776 ULONG SclkDpmThrottleMargin;
5779 ULONG ulBoostEngineCLock;
5786 ULONG ulReserved3[15];
5900 ULONG ulPowerplayTable[128];
5907 ULONG uReserved:2;
5908 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5909 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5910 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5912 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5913 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5914 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5915 ULONG uReserved:2;
5922 ULONG TDP_config_all;
5935 ULONG ulBootUpEngineClock;
5936 ULONG ulDentistVCOFreq;
5937 ULONG ulBootUpUMAClock;
5939 ULONG ulBootUpReqDisplayVector;
5940 ULONG ulOtherDisplayMisc;
5941 ULONG ulGPUCapInfo;
5942 ULONG ulSB_MMIO_Base_Addr;
5946 ULONG ulMinEngineClock;
5947 ULONG ulSystemConfig;
5948 ULONG ulCPUCapInfo;
5958 ULONG ulReserved[19];
5960 ULONG ulGMCRestoreResetTime;
5961 ULONG ulMinimumNClk;
5962 ULONG ulIdleNClk;
5963 ULONG ulDDR_DLL_PowerUpTime;
5964 ULONG ulDDR_PLL_PowerUpTime;
5973 ULONG SclkDpmBoostMargin;
5974 ULONG SclkDpmThrottleMargin;
5977 ULONG ulBoostEngineCLock;
5992 ULONG ulLCDBitDepthControlVal;
5993 ULONG ulNbpStateMemclkFreq[4];
5996 ULONG ulNbpStateNClkFreq[4];
6167 ULONG ulBootUpEngineClock;
6168 ULONG ulDentistVCOFreq;
6169 ULONG ulBootUpUMAClock;
6171 ULONG ulBootUpReqDisplayVector;
6172 ULONG ulVBIOSMisc;
6173 ULONG ulGPUCapInfo;
6174 ULONG ulDISP_CLK2Freq;
6178 ULONG ulReserved2;
6179 ULONG ulSystemConfig;
6180 ULONG ulCPUCapInfo;
6181 ULONG ulReserved3;
6189 ULONG ulReserved[19];
6191 ULONG ulGMCRestoreResetTime;
6192 ULONG ulReserved4;
6193 ULONG ulIdleNClk;
6194 ULONG ulDDR_DLL_PowerUpTime;
6195 ULONG ulDDR_PLL_PowerUpTime;
6204 ULONG ulGPUReservedSysMemBaseAddrLo;
6205 ULONG ulGPUReservedSysMemBaseAddrHi;
6207 ULONG ulReserved5;
6219 ULONG ulLCDBitDepthControlVal;
6220 ULONG ulNbpStateMemclkFreq[4];
6221 ULONG ulPSPVersion;
6222 ULONG ulNbpStateNClkFreq[4];
6385 ULONG ulBootUpEngineClock;
6386 ULONG ulDentistVCOFreq;
6387 ULONG ulBootUpUMAClock;
6389 ULONG ulBootUpReqDisplayVector;
6390 ULONG ulVBIOSMisc;
6391 ULONG ulGPUCapInfo;
6392 ULONG ulDISP_CLK2Freq;
6396 ULONG ulReserved2;
6397 ULONG ulSystemConfig;
6398 ULONG ulCPUCapInfo;
6399 ULONG ulReserved3;
6410 ULONG ulReserved[2];
6413 ULONG ulGMCRestoreResetTime;
6414 ULONG ulReserved4;
6415 ULONG ulIdleNClk;
6416 ULONG ulDDR_DLL_PowerUpTime;
6417 ULONG ulDDR_PLL_PowerUpTime;
6426 ULONG ulGPUReservedSysMemBaseAddrLo;
6427 ULONG ulGPUReservedSysMemBaseAddrHi;
6428 ULONG ulReserved5[3];
6440 ULONG ulLCDBitDepthControlVal;
6441 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6442 ULONG ulPSPVersion;
6443 ULONG ulNbpStateNClkFreq[4];
6475 ULONG ucPara;
6498 ULONG ulVersionCode;
6502 ULONG ulCrcVal; // CRC
6508 ULONG ulBootUpEngineClock;
6509 ULONG ulDentistVCOFreq;
6510 ULONG ulBootUpUMAClock;
6511 ULONG ulReserved0[8];
6512 ULONG ulBootUpReqDisplayVector;
6513 ULONG ulVBIOSMisc;
6514 ULONG ulGPUCapInfo;
6515 ULONG ulReserved1;
6519 ULONG ulReserved2;
6520 ULONG ulSystemConfig;
6521 ULONG ulCPUCapInfo;
6522 ULONG ulReserved3;
6528 ULONG ulMsgReserved[10];
6530 ULONG ulReserved[7];
6532 ULONG ulReserved6[10];
6533 ULONG ulGMCRestoreResetTime;
6534 ULONG ulReserved4;
6535 ULONG ulIdleNClk;
6536 ULONG ulDDR_DLL_PowerUpTime;
6537 ULONG ulDDR_PLL_PowerUpTime;
6546 ULONG ulGPUReservedSysMemBaseAddrLo;
6547 ULONG ulGPUReservedSysMemBaseAddrHi;
6548 ULONG ulReserved5[3];
6560 ULONG ulLCDBitDepthControlVal;
6561 ULONG ulNbpStateMemclkFreq[2];
6562 ULONG ulReserved7[2];
6563 ULONG ulPSPVersion;
6564 ULONG ulNbpStateNClkFreq[4];
6571 ULONG ulReserved8[29];
6579 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
6586 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable
6631 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6656 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6687 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
7171 ULONG ulTargetMemoryClock; //In 10Khz unit
7209 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
7348 ULONG ulEfuseValue;
7445 ULONG ulDllResetClkRange;
7451 ULONG ucMemBlkId:8;
7452 ULONG ulMemClockRange:24;
7454 ULONG ulMemClockRange:24;
7455 ULONG ucMemBlkId:8;
7462 ULONG ulAccess;
7468 ULONG aulMemData[1];
7490 #define VALUE_DWORD SIZEOF ULONG
7508 ULONG ulARB_SEQDataBuf[32];
7517 ULONG ulRegValue;
7523 ULONG ulMCUcodeVersion;
7524 ULONG ulMCUcodeRomStartAddr;
7525 ULONG ulMCUcodeLength;
7583 ULONG ulSignature;
7601 ULONG ulReserved;
7623 ULONG ulReserved;
7624 ULONG ulFlags; // To enable/disable functionalities based on memory type
7625 ULONG ulEngineClock; // Override of default engine clock for particular memory type
7626 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
7651 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7687 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7723 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7760 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
7787 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7809 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7851 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7883 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7915 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7946 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7970 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7971 ULONG ulBankMapCfg;
7972 ULONG ulReserved;
8006 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
8048 ULONG ulByte0BitRemapCh0;
8049 ULONG ulByte1BitRemapCh0;
8050 ULONG ulByte2BitRemapCh0;
8051 ULONG ulByte3BitRemapCh0;
8052 ULONG ulByte0BitRemapCh1;
8053 ULONG ulByte1BitRemapCh1;
8054 ULONG ulByte2BitRemapCh1;
8055 ULONG ulByte3BitRemapCh1;
8077 ULONG ulMCUcodeVersion;
8081 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.
8140 ULONG Ptr32_Bit;
8185 ULONG RsvdOffScrnMemSize;
8186 ULONG RsvdOffScrnMEmPtr;
8200 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8228 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8244 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8524 ULONG ulReserved;
8531 ULONG ulReserved;
8620 ULONG ulAnalogSetting[1];
8629 ULONG ulCondition;
8630 ULONG ulRegVal;
8634 ULONG ulCondition;
8636 ULONG ulRegVal;
8996 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8997 ULONG ulReserved1; // must set to 0
8998 ULONG ulReserved2; // must set to 0
9012 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9013 ULONG ulMiscInfo2;
9014 ULONG ulEngineClock;
9015 ULONG ulMemoryClock;
9027 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9028 ULONG ulMiscInfo2;
9029 ULONG ulEngineClock;
9030 ULONG ulMemoryClock;
9248 ULONG Signature;
9249 ULONG TableLength; //Length
9254 ULONG OemRevision;
9255 ULONG CreatorId;
9256 ULONG CreatorRevision;
9275 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
9276 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
9277 ULONG Reserved[4]; //0x3C
9281 ULONG PCIBus; //0x4C
9282 ULONG PCIDevice; //0x50
9283 ULONG PCIFunction; //0x54
9288 ULONG Revision; //0x60
9289 ULONG ImageLength; //0x64