1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24/****************************************************************************/ 25/*Portion I: Definitions shared between VBIOS and Driver */ 26/****************************************************************************/ 27 28#ifndef _ATOMBIOS_H 29#define _ATOMBIOS_H 30 31#define ATOM_VERSION_MAJOR 0x00020000 32#define ATOM_VERSION_MINOR 0x00000002 33 34#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 35 36/* Endianness should be specified before inclusion, 37 * default to little endian 38 */ 39#ifndef ATOM_BIG_ENDIAN 40#error Endian not specified 41#endif 42 43#ifdef _H2INC 44 #ifndef ULONG 45 typedef unsigned long ULONG; 46 #endif 47 48 #ifndef UCHAR 49 typedef unsigned char UCHAR; 50 #endif 51 52 #ifndef USHORT 53 typedef unsigned short USHORT; 54 #endif 55#endif 56 57#define ATOM_DAC_A 0 58#define ATOM_DAC_B 1 59#define ATOM_EXT_DAC 2 60 61#define ATOM_CRTC1 0 62#define ATOM_CRTC2 1 63#define ATOM_CRTC3 2 64#define ATOM_CRTC4 3 65#define ATOM_CRTC5 4 66#define ATOM_CRTC6 5 67 68#define ATOM_UNDERLAY_PIPE0 16 69#define ATOM_UNDERLAY_PIPE1 17 70 71#define ATOM_CRTC_INVALID 0xFF 72 73#define ATOM_DIGA 0 74#define ATOM_DIGB 1 75 76#define ATOM_PPLL1 0 77#define ATOM_PPLL2 1 78#define ATOM_DCPLL 2 79#define ATOM_PPLL0 2 80#define ATOM_PPLL3 3 81 82#define ATOM_PHY_PLL0 4 83#define ATOM_PHY_PLL1 5 84 85#define ATOM_EXT_PLL1 8 86#define ATOM_GCK_DFS 8 87#define ATOM_EXT_PLL2 9 88#define ATOM_FCH_CLK 9 89#define ATOM_EXT_CLOCK 10 90#define ATOM_DP_DTO 11 91 92#define ATOM_COMBOPHY_PLL0 20 93#define ATOM_COMBOPHY_PLL1 21 94#define ATOM_COMBOPHY_PLL2 22 95#define ATOM_COMBOPHY_PLL3 23 96#define ATOM_COMBOPHY_PLL4 24 97#define ATOM_COMBOPHY_PLL5 25 98 99#define ATOM_PPLL_INVALID 0xFF 100 101#define ENCODER_REFCLK_SRC_P1PLL 0 102#define ENCODER_REFCLK_SRC_P2PLL 1 103#define ENCODER_REFCLK_SRC_DCPLL 2 104#define ENCODER_REFCLK_SRC_EXTCLK 3 105#define ENCODER_REFCLK_SRC_INVALID 0xFF 106 107#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 108#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 109#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 110#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 111 112#define ATOM_DISABLE 0 113#define ATOM_ENABLE 1 114#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 115#define ATOM_LCD_BLON (ATOM_ENABLE+2) 116#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 117#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 118#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 119#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 120#define ATOM_INIT (ATOM_DISABLE+7) 121#define ATOM_GET_STATUS (ATOM_DISABLE+8) 122 123#define ATOM_BLANKING 1 124#define ATOM_BLANKING_OFF 0 125 126 127#define ATOM_CRT1 0 128#define ATOM_CRT2 1 129 130#define ATOM_TV_NTSC 1 131#define ATOM_TV_NTSCJ 2 132#define ATOM_TV_PAL 3 133#define ATOM_TV_PALM 4 134#define ATOM_TV_PALCN 5 135#define ATOM_TV_PALN 6 136#define ATOM_TV_PAL60 7 137#define ATOM_TV_SECAM 8 138#define ATOM_TV_CV 16 139 140#define ATOM_DAC1_PS2 1 141#define ATOM_DAC1_CV 2 142#define ATOM_DAC1_NTSC 3 143#define ATOM_DAC1_PAL 4 144 145#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 146#define ATOM_DAC2_CV ATOM_DAC1_CV 147#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 148#define ATOM_DAC2_PAL ATOM_DAC1_PAL 149 150#define ATOM_PM_ON 0 151#define ATOM_PM_STANDBY 1 152#define ATOM_PM_SUSPEND 2 153#define ATOM_PM_OFF 3 154 155// For ATOM_LVDS_INFO_V12 156// Bit0:{=0:single, =1:dual}, 157// Bit1 {=0:666RGB, =1:888RGB}, 158// Bit2:3:{Grey level} 159// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 160#define ATOM_PANEL_MISC_DUAL 0x00000001 161#define ATOM_PANEL_MISC_888RGB 0x00000002 162#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 163#define ATOM_PANEL_MISC_FPDI 0x00000010 164#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 165#define ATOM_PANEL_MISC_SPATIAL 0x00000020 166#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 167#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 168 169#define MEMTYPE_DDR1 "DDR1" 170#define MEMTYPE_DDR2 "DDR2" 171#define MEMTYPE_DDR3 "DDR3" 172#define MEMTYPE_DDR4 "DDR4" 173 174#define ASIC_BUS_TYPE_PCI "PCI" 175#define ASIC_BUS_TYPE_AGP "AGP" 176#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 177 178//Maximum size of that FireGL flag string 179#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 180#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 181 182#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 183#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 184 185#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 186#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 187 188#define HW_ASSISTED_I2C_STATUS_FAILURE 2 189#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 190 191#pragma pack(1) // BIOS data must use byte alignment 192 193// Define offset to location of ROM header. 194#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 195#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 196 197#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 198#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 199#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 200#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 201 202/****************************************************************************/ 203// Common header for all tables (Data table, Command table). 204// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 205// And the pointer actually points to this header. 206/****************************************************************************/ 207 208typedef struct _ATOM_COMMON_TABLE_HEADER 209{ 210 USHORT usStructureSize; 211 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 212 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 213 //Image can't be updated, while Driver needs to carry the new table! 214}ATOM_COMMON_TABLE_HEADER; 215 216/****************************************************************************/ 217// Structure stores the ROM header. 218/****************************************************************************/ 219typedef struct _ATOM_ROM_HEADER 220{ 221 ATOM_COMMON_TABLE_HEADER sHeader; 222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 223 //atombios should init it as "ATOM", don't change the position 224 USHORT usBiosRuntimeSegmentAddress; 225 USHORT usProtectedModeInfoOffset; 226 USHORT usConfigFilenameOffset; 227 USHORT usCRC_BlockOffset; 228 USHORT usBIOS_BootupMessageOffset; 229 USHORT usInt10Offset; 230 USHORT usPciBusDevInitCode; 231 USHORT usIoBaseAddress; 232 USHORT usSubsystemVendorID; 233 USHORT usSubsystemID; 234 USHORT usPCI_InfoOffset; 235 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 236 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 237 UCHAR ucExtendedFunctionCode; 238 UCHAR ucReserved; 239}ATOM_ROM_HEADER; 240 241 242typedef struct _ATOM_ROM_HEADER_V2_1 243{ 244 ATOM_COMMON_TABLE_HEADER sHeader; 245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 246 //atombios should init it as "ATOM", don't change the position 247 USHORT usBiosRuntimeSegmentAddress; 248 USHORT usProtectedModeInfoOffset; 249 USHORT usConfigFilenameOffset; 250 USHORT usCRC_BlockOffset; 251 USHORT usBIOS_BootupMessageOffset; 252 USHORT usInt10Offset; 253 USHORT usPciBusDevInitCode; 254 USHORT usIoBaseAddress; 255 USHORT usSubsystemVendorID; 256 USHORT usSubsystemID; 257 USHORT usPCI_InfoOffset; 258 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 259 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 260 UCHAR ucExtendedFunctionCode; 261 UCHAR ucReserved; 262 ULONG ulPSPDirTableOffset; 263}ATOM_ROM_HEADER_V2_1; 264 265 266//==============================Command Table Portion==================================== 267 268 269/****************************************************************************/ 270// Structures used in Command.mtb 271/****************************************************************************/ 272typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 273 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 274 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 275 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 276 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 277 USHORT DIGxEncoderControl; //Only used by Bios 278 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 279 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 280 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 281 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 282 USHORT GPIOPinControl; //Atomic Table, only used by Bios 283 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 284 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 285 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 286 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 287 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 288 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 289 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 290 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 291 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 292 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 293 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 294 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 295 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 296 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 297 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 298 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 299 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 300 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 301 USHORT GetConditionalGoldenSetting; //Only used by Bios 302 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 303 USHORT PatchMCSetting; //only used by BIOS 304 USHORT MC_SEQ_Control; //only used by BIOS 305 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 306 USHORT EnableScaler; //Atomic Table, used only by Bios 307 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 308 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 309 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 310 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 311 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 312 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 314 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios 315 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 316 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 317 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 318 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 319 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK 320 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 321 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 322 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 323 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 324 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 325 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 326 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 327 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 328 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 329 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 330 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 331 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 332 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 333 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 334 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 335 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 336 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 337 USHORT MemoryTraining; //Atomic Table, used only by Bios 338 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 339 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 340 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 341 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 342 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 343 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 344 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 345 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 346 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 347 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 348 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 349 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 350 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 351 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 352 USHORT DPEncoderService; //Function Table,only used by Bios 353 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 354}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 355 356// For backward compatible 357#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 358#define DPTranslatorControl DIG2EncoderControl 359#define UNIPHYTransmitterControl DIG1TransmitterControl 360#define LVTMATransmitterControl DIG2TransmitterControl 361#define SetCRTC_DPM_State GetConditionalGoldenSetting 362#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 363#define HPDInterruptService ReadHWAssistedI2CStatus 364#define EnableVGA_Access GetSCLKOverMCLKRatio 365#define EnableYUV GetDispObjectInfo 366#define DynamicClockGating EnableDispPowerGating 367#define SetupHWAssistedI2CStatus ComputeMemoryClockParam 368#define DAC2OutputControl ReadEfuseValue 369 370#define TMDSAEncoderControl PatchMCSetting 371#define LVDSEncoderControl MC_SEQ_Control 372#define LCD1OutputControl HW_Misc_Operation 373#define TV1OutputControl Gfx_Harvesting 374#define TVEncoderControl SMC_Init 375#define EnableHW_IconCursor SetDCEClock 376#define SetCRTC_Replication GetSMUClockInfo 377 378#define MemoryRefreshConversion Gfx_Init 379 380typedef struct _ATOM_MASTER_COMMAND_TABLE 381{ 382 ATOM_COMMON_TABLE_HEADER sHeader; 383 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 384}ATOM_MASTER_COMMAND_TABLE; 385 386/****************************************************************************/ 387// Structures used in every command table 388/****************************************************************************/ 389typedef struct _ATOM_TABLE_ATTRIBUTE 390{ 391#if ATOM_BIG_ENDIAN 392 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 393 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 394 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 395#else 396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 397 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 398 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 399#endif 400}ATOM_TABLE_ATTRIBUTE; 401 402/****************************************************************************/ 403// Common header for all command tables. 404// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 405// And the pointer actually points to this header. 406/****************************************************************************/ 407typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 408{ 409 ATOM_COMMON_TABLE_HEADER CommonHeader; 410 ATOM_TABLE_ATTRIBUTE TableAttribute; 411}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 412 413/****************************************************************************/ 414// Structures used by ComputeMemoryEnginePLLTable 415/****************************************************************************/ 416 417#define COMPUTE_MEMORY_PLL_PARAM 1 418#define COMPUTE_ENGINE_PLL_PARAM 2 419#define ADJUST_MC_SETTING_PARAM 3 420 421/****************************************************************************/ 422// Structures used by AdjustMemoryControllerTable 423/****************************************************************************/ 424typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 425{ 426#if ATOM_BIG_ENDIAN 427 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 429 ULONG ulClockFreq:24; 430#else 431 ULONG ulClockFreq:24; 432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 433 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 434#endif 435}ATOM_ADJUST_MEMORY_CLOCK_FREQ; 436#define POINTER_RETURN_FLAG 0x80 437 438typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 439{ 440 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 442 UCHAR ucReserved; //may expand to return larger Fbdiv later 443 UCHAR ucFbDiv; //return value 444 UCHAR ucPostDiv; //return value 445}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 446 447typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 448{ 449 ULONG ulClock; //When return, [23:0] return real clock 450 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 451 USHORT usFbDiv; //return Feedback value to be written to register 452 UCHAR ucPostDiv; //return post div to be written to register 453}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 454 455#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 456 457#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 458#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 459#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 460#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 461#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 462#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 463#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 464 465#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 466#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 467#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 468#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 469#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 470#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 471#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 472#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 473#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only 474 475typedef struct _ATOM_COMPUTE_CLOCK_FREQ 476{ 477#if ATOM_BIG_ENDIAN 478 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 479 ULONG ulClockFreq:24; // in unit of 10kHz 480#else 481 ULONG ulClockFreq:24; // in unit of 10kHz 482 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 483#endif 484}ATOM_COMPUTE_CLOCK_FREQ; 485 486typedef struct _ATOM_S_MPLL_FB_DIVIDER 487{ 488 USHORT usFbDivFrac; 489 USHORT usFbDiv; 490}ATOM_S_MPLL_FB_DIVIDER; 491 492typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 493{ 494 union 495 { 496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 497 ULONG ulClockParams; //ULONG access for BE 498 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 499 }; 500 UCHAR ucRefDiv; //Output Parameter 501 UCHAR ucPostDiv; //Output Parameter 502 UCHAR ucCntlFlag; //Output Parameter 503 UCHAR ucReserved; 504}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 505 506// ucCntlFlag 507#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 508#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 509#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 510#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 511 512 513// V4 are only used for APU which PLL outside GPU 514typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 515{ 516#if ATOM_BIG_ENDIAN 517 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 518 ULONG ulClock:24; //Input= target clock, output = actual clock 519#else 520 ULONG ulClock:24; //Input= target clock, output = actual clock 521 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 522#endif 523}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 524 525typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 526{ 527 union 528 { 529 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 530 ULONG ulClockParams; //ULONG access for BE 531 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 532 }; 533 UCHAR ucRefDiv; //Output Parameter 534 UCHAR ucPostDiv; //Output Parameter 535 union 536 { 537 UCHAR ucCntlFlag; //Output Flags 538 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 539 }; 540 UCHAR ucReserved; 541}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 542 543 544typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 545{ 546 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 547 ULONG ulReserved[2]; 548}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 549 550//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 551#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 552#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 553#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 554 555 556typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 557{ 558 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 559 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 560 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 561 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 562 UCHAR ucPllCntlFlag; //Output Flags: control flag 563 UCHAR ucReserved; 564}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 565 566//ucPllCntlFlag 567#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 568 569typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 570{ 571 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 572 ULONG ulReserved[5]; 573}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; 574 575//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 576#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 577#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 578#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 579 580typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 581{ 582 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 583 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 584 USHORT usSclk_fcw_int; //integer divider of fcwc 585 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv 586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved 587 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 ) 588 UCHAR ucSscEnable; 589 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable 590 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable 591 USHORT usReserved; 592 USHORT usPcc_fcw_int; 593 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable 594 USHORT usPcc_fcw_slew_frac; 595}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; 596 597// ucInputFlag 598#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 599 600// use for ComputeMemoryClockParamTable 601typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 602{ 603 union 604 { 605 ULONG ulClock; 606 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 607 }; 608 UCHAR ucDllSpeed; //Output 609 UCHAR ucPostDiv; //Output 610 union{ 611 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 612 UCHAR ucPllCntlFlag; //Output: 613 }; 614 UCHAR ucBWCntl; 615}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 616 617// definition of ucInputFlag 618#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 619// definition of ucPllCntlFlag 620#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 621#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 622#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 623#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 624 625//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 626#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 627 628// use for ComputeMemoryClockParamTable 629typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 630{ 631 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 632 ULONG ulReserved; 633}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; 634 635typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 636{ 637 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 638 USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 639 USHORT usMclk_fcw_int; //integer divider of fcwc 640}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3; 641 642//Input parameter of DynamicMemorySettingsTable 643//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM 644typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 645{ 646 ATOM_COMPUTE_CLOCK_FREQ ulClock; 647 ULONG ulReserved[2]; 648}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 649 650//Input parameter of DynamicMemorySettingsTable 651//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM 652typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 653{ 654 ATOM_COMPUTE_CLOCK_FREQ ulClock; 655 ULONG ulMemoryClock; 656 ULONG ulReserved; 657}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 658 659//Input parameter of DynamicMemorySettingsTable ver2.1 and above 660//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM 661typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER 662{ 663 ATOM_COMPUTE_CLOCK_FREQ ulClock; 664 UCHAR ucMclkDPMState; 665 UCHAR ucReserved[3]; 666 ULONG ulReserved; 667}DYNAMICE_MC_DPM_SETTINGS_PARAMETER; 668 669//ucMclkDPMState 670#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0 671#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1 672#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2 673 674typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 675{ 676 DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg; 677 DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg; 678 DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg; 679}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; 680 681 682/****************************************************************************/ 683// Structures used by SetEngineClockTable 684/****************************************************************************/ 685typedef struct _SET_ENGINE_CLOCK_PARAMETERS 686{ 687 ULONG ulTargetEngineClock; //In 10Khz unit 688}SET_ENGINE_CLOCK_PARAMETERS; 689 690typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 691{ 692 ULONG ulTargetEngineClock; //In 10Khz unit 693 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 694}SET_ENGINE_CLOCK_PS_ALLOCATION; 695 696typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 697{ 698 ULONG ulTargetEngineClock; //In 10Khz unit 699 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved; 700}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; 701 702 703/****************************************************************************/ 704// Structures used by SetMemoryClockTable 705/****************************************************************************/ 706typedef struct _SET_MEMORY_CLOCK_PARAMETERS 707{ 708 ULONG ulTargetMemoryClock; //In 10Khz unit 709}SET_MEMORY_CLOCK_PARAMETERS; 710 711typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 712{ 713 ULONG ulTargetMemoryClock; //In 10Khz unit 714 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 715}SET_MEMORY_CLOCK_PS_ALLOCATION; 716 717/****************************************************************************/ 718// Structures used by ASIC_Init.ctb 719/****************************************************************************/ 720typedef struct _ASIC_INIT_PARAMETERS 721{ 722 ULONG ulDefaultEngineClock; //In 10Khz unit 723 ULONG ulDefaultMemoryClock; //In 10Khz unit 724}ASIC_INIT_PARAMETERS; 725 726typedef struct _ASIC_INIT_PS_ALLOCATION 727{ 728 ASIC_INIT_PARAMETERS sASICInitClocks; 729 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 730}ASIC_INIT_PS_ALLOCATION; 731 732typedef struct _ASIC_INIT_CLOCK_PARAMETERS 733{ 734 ULONG ulClkFreqIn10Khz:24; 735 ULONG ucClkFlag:8; 736}ASIC_INIT_CLOCK_PARAMETERS; 737 738typedef struct _ASIC_INIT_PARAMETERS_V1_2 739{ 740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 741 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 742}ASIC_INIT_PARAMETERS_V1_2; 743 744typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 745{ 746 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 747 ULONG ulReserved[8]; 748}ASIC_INIT_PS_ALLOCATION_V1_2; 749 750/****************************************************************************/ 751// Structure used by DynamicClockGatingTable.ctb 752/****************************************************************************/ 753typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 754{ 755 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 756 UCHAR ucPadding[3]; 757}DYNAMIC_CLOCK_GATING_PARAMETERS; 758#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 759 760/****************************************************************************/ 761// Structure used by EnableDispPowerGatingTable.ctb 762/****************************************************************************/ 763typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 764{ 765 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 766 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 767 UCHAR ucPadding[2]; 768}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 769 770typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 771{ 772 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 773 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 774 UCHAR ucPadding[2]; 775 ULONG ulReserved[4]; 776}ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 777 778/****************************************************************************/ 779// Structure used by EnableASIC_StaticPwrMgtTable.ctb 780/****************************************************************************/ 781typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 782{ 783 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 784 UCHAR ucPadding[3]; 785}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 786#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 787 788/****************************************************************************/ 789// Structures used by DAC_LoadDetectionTable.ctb 790/****************************************************************************/ 791typedef struct _DAC_LOAD_DETECTION_PARAMETERS 792{ 793 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 794 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 795 UCHAR ucMisc; //Valid only when table revision =1.3 and above 796}DAC_LOAD_DETECTION_PARAMETERS; 797 798// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 799#define DAC_LOAD_MISC_YPrPb 0x01 800 801typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 802{ 803 DAC_LOAD_DETECTION_PARAMETERS sDacload; 804 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 805}DAC_LOAD_DETECTION_PS_ALLOCATION; 806 807/****************************************************************************/ 808// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 809/****************************************************************************/ 810typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 811{ 812 USHORT usPixelClock; // in 10KHz; for bios convenient 813 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 814 UCHAR ucAction; // 0: turn off encoder 815 // 1: setup and turn on encoder 816 // 7: ATOM_ENCODER_INIT Initialize DAC 817}DAC_ENCODER_CONTROL_PARAMETERS; 818 819#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 820 821/****************************************************************************/ 822// Structures used by DIG1EncoderControlTable 823// DIG2EncoderControlTable 824// ExternalEncoderControlTable 825/****************************************************************************/ 826typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 827{ 828 USHORT usPixelClock; // in 10KHz; for bios convenient 829 UCHAR ucConfig; 830 // [2] Link Select: 831 // =0: PHY linkA if bfLane<3 832 // =1: PHY linkB if bfLanes<3 833 // =0: PHY linkA+B if bfLanes=3 834 // [3] Transmitter Sel 835 // =0: UNIPHY or PCIEPHY 836 // =1: LVTMA 837 UCHAR ucAction; // =0: turn off encoder 838 // =1: turn on encoder 839 UCHAR ucEncoderMode; 840 // =0: DP encoder 841 // =1: LVDS encoder 842 // =2: DVI encoder 843 // =3: HDMI encoder 844 // =4: SDVO encoder 845 UCHAR ucLaneNum; // how many lanes to enable 846 UCHAR ucReserved[2]; 847}DIG_ENCODER_CONTROL_PARAMETERS; 848#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 849#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 850 851//ucConfig 852#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 853#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 854#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 855#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 856#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 857#define ATOM_ENCODER_CONFIG_LINKA 0x00 858#define ATOM_ENCODER_CONFIG_LINKB 0x04 859#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 860#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 861#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 862#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 863#define ATOM_ENCODER_CONFIG_LVTMA 0x08 864#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 865#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 866#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 867// ucAction 868// ATOM_ENABLE: Enable Encoder 869// ATOM_DISABLE: Disable Encoder 870 871//ucEncoderMode 872#define ATOM_ENCODER_MODE_DP 0 873#define ATOM_ENCODER_MODE_LVDS 1 874#define ATOM_ENCODER_MODE_DVI 2 875#define ATOM_ENCODER_MODE_HDMI 3 876#define ATOM_ENCODER_MODE_SDVO 4 877#define ATOM_ENCODER_MODE_DP_AUDIO 5 878#define ATOM_ENCODER_MODE_TV 13 879#define ATOM_ENCODER_MODE_CV 14 880#define ATOM_ENCODER_MODE_CRT 15 881#define ATOM_ENCODER_MODE_DVO 16 882#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 883#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 884 885 886typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 887{ 888#if ATOM_BIG_ENDIAN 889 UCHAR ucReserved1:2; 890 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 891 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 892 UCHAR ucReserved:1; 893 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 894#else 895 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 896 UCHAR ucReserved:1; 897 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 898 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 899 UCHAR ucReserved1:2; 900#endif 901}ATOM_DIG_ENCODER_CONFIG_V2; 902 903 904typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 905{ 906 USHORT usPixelClock; // in 10KHz; for bios convenient 907 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 908 UCHAR ucAction; 909 UCHAR ucEncoderMode; 910 // =0: DP encoder 911 // =1: LVDS encoder 912 // =2: DVI encoder 913 // =3: HDMI encoder 914 // =4: SDVO encoder 915 UCHAR ucLaneNum; // how many lanes to enable 916 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 917 UCHAR ucReserved; 918}DIG_ENCODER_CONTROL_PARAMETERS_V2; 919 920//ucConfig 921#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 922#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 923#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 924#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 925#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 926#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 927#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 928#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 929#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 930#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 931 932// ucAction: 933// ATOM_DISABLE 934// ATOM_ENABLE 935#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 936#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 937#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 938#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 939#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 940#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 941#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 942#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 943#define ATOM_ENCODER_CMD_SETUP 0x0f 944#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 945 946// New Command for DIGxEncoderControlTable v1.5 947#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 948#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP 949#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table 950#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table 951 952// ucStatus 953#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 954#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 955 956//ucTableFormatRevision=1 957//ucTableContentRevision=3 958// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 959typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 960{ 961#if ATOM_BIG_ENDIAN 962 UCHAR ucReserved1:1; 963 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 964 UCHAR ucReserved:3; 965 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 966#else 967 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 968 UCHAR ucReserved:3; 969 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 970 UCHAR ucReserved1:1; 971#endif 972}ATOM_DIG_ENCODER_CONFIG_V3; 973 974#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 975#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 976#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 977#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 978#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 979#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 980#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 981#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 982#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 983#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 984 985typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 986{ 987 USHORT usPixelClock; // in 10KHz; for bios convenient 988 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 989 UCHAR ucAction; 990 union{ 991 UCHAR ucEncoderMode; 992 // =0: DP encoder 993 // =1: LVDS encoder 994 // =2: DVI encoder 995 // =3: HDMI encoder 996 // =4: SDVO encoder 997 // =5: DP audio 998 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 999 // =0: external DP 1000 // =0x1: internal DP2 1001 // =0x11: internal DP1 for NutMeg/Travis DP translator 1002 }; 1003 UCHAR ucLaneNum; // how many lanes to enable 1004 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1005 UCHAR ucReserved; 1006}DIG_ENCODER_CONTROL_PARAMETERS_V3; 1007 1008//ucTableFormatRevision=1 1009//ucTableContentRevision=4 1010// start from NI 1011// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 1012typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 1013{ 1014#if ATOM_BIG_ENDIAN 1015 UCHAR ucReserved1:1; 1016 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1017 UCHAR ucReserved:2; 1018 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1019#else 1020 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1021 UCHAR ucReserved:2; 1022 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1023 UCHAR ucReserved1:1; 1024#endif 1025}ATOM_DIG_ENCODER_CONFIG_V4; 1026 1027#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 1028#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 1029#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 1030#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 1031#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 1032#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 1033#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 1034#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 1035#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 1036#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 1037#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 1038#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 1039#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 1040 1041typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 1042{ 1043 USHORT usPixelClock; // in 10KHz; for bios convenient 1044 union{ 1045 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 1046 UCHAR ucConfig; 1047 }; 1048 UCHAR ucAction; 1049 union{ 1050 UCHAR ucEncoderMode; 1051 // =0: DP encoder 1052 // =1: LVDS encoder 1053 // =2: DVI encoder 1054 // =3: HDMI encoder 1055 // =4: SDVO encoder 1056 // =5: DP audio 1057 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1058 // =0: external DP 1059 // =0x1: internal DP2 1060 // =0x11: internal DP1 for NutMeg/Travis DP translator 1061 }; 1062 UCHAR ucLaneNum; // how many lanes to enable 1063 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1064 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 1065}DIG_ENCODER_CONTROL_PARAMETERS_V4; 1066 1067// define ucBitPerColor: 1068#define PANEL_BPC_UNDEFINE 0x00 1069#define PANEL_6BIT_PER_COLOR 0x01 1070#define PANEL_8BIT_PER_COLOR 0x02 1071#define PANEL_10BIT_PER_COLOR 0x03 1072#define PANEL_12BIT_PER_COLOR 0x04 1073#define PANEL_16BIT_PER_COLOR 0x05 1074 1075//define ucPanelMode 1076#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 1077#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 1078#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 1079 1080 1081typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5 1082{ 1083 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1084 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP 1085 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1086 UCHAR ucLaneNum; // Lane number 1087 ULONG ulPixelClock; // Pixel Clock in 10Khz 1088 UCHAR ucBitPerColor; 1089 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 1090 UCHAR ucReserved[2]; 1091}ENCODER_STREAM_SETUP_PARAMETERS_V5; 1092 1093typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5 1094{ 1095 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1096 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP 1097 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1098 UCHAR ucLaneNum; // Lane number 1099 ULONG ulSymClock; // Symbol Clock in 10Khz 1100 UCHAR ucHPDSel; 1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1102 UCHAR ucReserved[2]; 1103}ENCODER_LINK_SETUP_PARAMETERS_V5; 1104 1105typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5 1106{ 1107 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1108 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP 1109 UCHAR ucPanelMode; // =0: external DP 1110 // =0x1: internal DP2 1111 // =0x11: internal DP1 NutMeg/Travis DP Translator 1112 UCHAR ucReserved; 1113 ULONG ulReserved[2]; 1114}DP_PANEL_MODE_SETUP_PARAMETERS_V5; 1115 1116typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5 1117{ 1118 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1119 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters 1120 UCHAR ucReserved[2]; 1121 ULONG ulReserved[2]; 1122}ENCODER_GENERIC_CMD_PARAMETERS_V5; 1123 1124//ucDigId 1125#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00 1126#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01 1127#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02 1128#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03 1129#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04 1130#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05 1131#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06 1132 1133 1134typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5 1135{ 1136 ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam; 1137 ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam; 1138 ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam; 1139 DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam; 1140}DIG_ENCODER_CONTROL_PARAMETERS_V5; 1141 1142 1143/****************************************************************************/ 1144// Structures used by UNIPHYTransmitterControlTable 1145// LVTMATransmitterControlTable 1146// DVOOutputControlTable 1147/****************************************************************************/ 1148typedef struct _ATOM_DP_VS_MODE 1149{ 1150 UCHAR ucLaneSel; 1151 UCHAR ucLaneSet; 1152}ATOM_DP_VS_MODE; 1153 1154typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 1155{ 1156 union 1157 { 1158 USHORT usPixelClock; // in 10KHz; for bios convenient 1159 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1160 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1161 }; 1162 UCHAR ucConfig; 1163 // [0]=0: 4 lane Link, 1164 // =1: 8 lane Link ( Dual Links TMDS ) 1165 // [1]=0: InCoherent mode 1166 // =1: Coherent Mode 1167 // [2] Link Select: 1168 // =0: PHY linkA if bfLane<3 1169 // =1: PHY linkB if bfLanes<3 1170 // =0: PHY linkA+B if bfLanes=3 1171 // [5:4]PCIE lane Sel 1172 // =0: lane 0~3 or 0~7 1173 // =1: lane 4~7 1174 // =2: lane 8~11 or 8~15 1175 // =3: lane 12~15 1176 UCHAR ucAction; // =0: turn off encoder 1177 // =1: turn on encoder 1178 UCHAR ucReserved[4]; 1179}DIG_TRANSMITTER_CONTROL_PARAMETERS; 1180 1181#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 1182 1183//ucInitInfo 1184#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 1185 1186//ucConfig 1187#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 1188#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 1189#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1190#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1191#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1192#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1193#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1194 1195#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1196#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1197#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1198 1199#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1200#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1201#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1202#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1203#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1204#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1205#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1206#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1207#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1208#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1209#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1210 1211//ucAction 1212#define ATOM_TRANSMITTER_ACTION_DISABLE 0 1213#define ATOM_TRANSMITTER_ACTION_ENABLE 1 1214#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1215#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1216#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1217#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1218#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1219#define ATOM_TRANSMITTER_ACTION_INIT 7 1220#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1221#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1222#define ATOM_TRANSMITTER_ACTION_SETUP 10 1223#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1224#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1225#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1226 1227// Following are used for DigTransmitterControlTable ver1.2 1228typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1229{ 1230#if ATOM_BIG_ENDIAN 1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1232 // =1 Dig Transmitter 2 ( Uniphy CD ) 1233 // =2 Dig Transmitter 3 ( Uniphy EF ) 1234 UCHAR ucReserved:1; 1235 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1236 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1237 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1238 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1239 1240 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1241 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1242#else 1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1244 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1245 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1246 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1247 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1248 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1249 UCHAR ucReserved:1; 1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1251 // =1 Dig Transmitter 2 ( Uniphy CD ) 1252 // =2 Dig Transmitter 3 ( Uniphy EF ) 1253#endif 1254}ATOM_DIG_TRANSMITTER_CONFIG_V2; 1255 1256//ucConfig 1257//Bit0 1258#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1259 1260//Bit1 1261#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1262 1263//Bit2 1264#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1265#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1266#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1267 1268// Bit3 1269#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1270#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1271#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1272 1273// Bit4 1274#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1275 1276// Bit7:6 1277#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1278#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1279#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1280#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1281 1282typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1283{ 1284 union 1285 { 1286 USHORT usPixelClock; // in 10KHz; for bios convenient 1287 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1288 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1289 }; 1290 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1291 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1292 UCHAR ucReserved[4]; 1293}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1294 1295typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1296{ 1297#if ATOM_BIG_ENDIAN 1298 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1299 // =1 Dig Transmitter 2 ( Uniphy CD ) 1300 // =2 Dig Transmitter 3 ( Uniphy EF ) 1301 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1302 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1303 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1304 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1305 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1306 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1307#else 1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1309 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1310 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1311 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1312 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1313 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1314 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1315 // =1 Dig Transmitter 2 ( Uniphy CD ) 1316 // =2 Dig Transmitter 3 ( Uniphy EF ) 1317#endif 1318}ATOM_DIG_TRANSMITTER_CONFIG_V3; 1319 1320 1321typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1322{ 1323 union 1324 { 1325 USHORT usPixelClock; // in 10KHz; for bios convenient 1326 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1327 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1328 }; 1329 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1330 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1331 UCHAR ucLaneNum; 1332 UCHAR ucReserved[3]; 1333}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1334 1335//ucConfig 1336//Bit0 1337#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1338 1339//Bit1 1340#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1341 1342//Bit2 1343#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1344#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1345#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1346 1347// Bit3 1348#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1349#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1350#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1351 1352// Bit5:4 1353#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1354#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1355#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1356#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1357 1358// Bit7:6 1359#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1360#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1361#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1362#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1363 1364 1365/****************************************************************************/ 1366// Structures used by UNIPHYTransmitterControlTable V1.4 1367// ASIC Families: NI 1368// ucTableFormatRevision=1 1369// ucTableContentRevision=4 1370/****************************************************************************/ 1371typedef struct _ATOM_DP_VS_MODE_V4 1372{ 1373 UCHAR ucLaneSel; 1374 union 1375 { 1376 UCHAR ucLaneSet; 1377 struct { 1378#if ATOM_BIG_ENDIAN 1379 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1381 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1382#else 1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1385 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1386#endif 1387 }; 1388 }; 1389}ATOM_DP_VS_MODE_V4; 1390 1391typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1392{ 1393#if ATOM_BIG_ENDIAN 1394 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1395 // =1 Dig Transmitter 2 ( Uniphy CD ) 1396 // =2 Dig Transmitter 3 ( Uniphy EF ) 1397 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1398 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1399 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1400 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1401 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1402 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1403#else 1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1405 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1406 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1407 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1408 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1409 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1410 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1411 // =1 Dig Transmitter 2 ( Uniphy CD ) 1412 // =2 Dig Transmitter 3 ( Uniphy EF ) 1413#endif 1414}ATOM_DIG_TRANSMITTER_CONFIG_V4; 1415 1416typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1417{ 1418 union 1419 { 1420 USHORT usPixelClock; // in 10KHz; for bios convenient 1421 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1422 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1423 }; 1424 union 1425 { 1426 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1427 UCHAR ucConfig; 1428 }; 1429 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1430 UCHAR ucLaneNum; 1431 UCHAR ucReserved[3]; 1432}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1433 1434//ucConfig 1435//Bit0 1436#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1437//Bit1 1438#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1439//Bit2 1440#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1441#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1442#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1443// Bit3 1444#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1445#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1446#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1447// Bit5:4 1448#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1449#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1450#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1451#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1452#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1453// Bit7:6 1454#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1455#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1456#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1457#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1458 1459 1460typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1461{ 1462#if ATOM_BIG_ENDIAN 1463 UCHAR ucReservd1:1; 1464 UCHAR ucHPDSel:3; 1465 UCHAR ucPhyClkSrcId:2; 1466 UCHAR ucCoherentMode:1; 1467 UCHAR ucReserved:1; 1468#else 1469 UCHAR ucReserved:1; 1470 UCHAR ucCoherentMode:1; 1471 UCHAR ucPhyClkSrcId:2; 1472 UCHAR ucHPDSel:3; 1473 UCHAR ucReservd1:1; 1474#endif 1475}ATOM_DIG_TRANSMITTER_CONFIG_V5; 1476 1477typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1478{ 1479 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1480 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1481 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1482 UCHAR ucLaneNum; // indicate lane number 1-8 1483 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1484 UCHAR ucDigMode; // indicate DIG mode 1485 union{ 1486 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1487 UCHAR ucConfig; 1488 }; 1489 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1490 UCHAR ucDPLaneSet; 1491 UCHAR ucReserved; 1492 UCHAR ucReserved1; 1493}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1494 1495//ucPhyId 1496#define ATOM_PHY_ID_UNIPHYA 0 1497#define ATOM_PHY_ID_UNIPHYB 1 1498#define ATOM_PHY_ID_UNIPHYC 2 1499#define ATOM_PHY_ID_UNIPHYD 3 1500#define ATOM_PHY_ID_UNIPHYE 4 1501#define ATOM_PHY_ID_UNIPHYF 5 1502#define ATOM_PHY_ID_UNIPHYG 6 1503 1504// ucDigEncoderSel 1505#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1506#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1507#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1508#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1509#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1510#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1511#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1512 1513// ucDigMode 1514#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1515#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1516#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1517#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1518#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1519#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1520 1521// ucDPLaneSet 1522#define DP_LANE_SET__0DB_0_4V 0x00 1523#define DP_LANE_SET__0DB_0_6V 0x01 1524#define DP_LANE_SET__0DB_0_8V 0x02 1525#define DP_LANE_SET__0DB_1_2V 0x03 1526#define DP_LANE_SET__3_5DB_0_4V 0x08 1527#define DP_LANE_SET__3_5DB_0_6V 0x09 1528#define DP_LANE_SET__3_5DB_0_8V 0x0a 1529#define DP_LANE_SET__6DB_0_4V 0x10 1530#define DP_LANE_SET__6DB_0_6V 0x11 1531#define DP_LANE_SET__9_5DB_0_4V 0x18 1532 1533// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1534// Bit1 1535#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1536 1537// Bit3:2 1538#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1539#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1540 1541#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1542#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1543#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1544#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1545// Bit6:4 1546#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1547#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1548 1549#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1550#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1551#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1552#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1553#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1554#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1555#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1556 1557#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1558 1559typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 1560{ 1561 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1562 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1563 union 1564 { 1565 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1566 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 1567 }; 1568 UCHAR ucLaneNum; // Lane number 1569 ULONG ulSymClock; // Symbol Clock in 10Khz 1570 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1572 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1573 UCHAR ucReserved; 1574 ULONG ulReserved; 1575}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; 1576 1577 1578// ucDigEncoderSel 1579#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01 1580#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02 1581#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04 1582#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08 1583#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10 1584#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20 1585#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40 1586 1587// ucDigMode 1588#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 1589#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 1590#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 1591#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 1592 1593//ucHPDSel 1594#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00 1595#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01 1596#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02 1597#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03 1598#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04 1599#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05 1600#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06 1601 1602 1603/****************************************************************************/ 1604// Structures used by ExternalEncoderControlTable V1.3 1605// ASIC Families: Evergreen, Llano, NI 1606// ucTableFormatRevision=1 1607// ucTableContentRevision=3 1608/****************************************************************************/ 1609 1610typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1611{ 1612 union{ 1613 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1614 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1615 }; 1616 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1617 UCHAR ucAction; // 1618 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1619 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1620 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1621 UCHAR ucReserved; 1622}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1623 1624// ucAction 1625#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1626#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1627#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1628#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1629#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1630#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1631#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1632#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1633 1634// ucConfig 1635#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1636#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1637#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1638#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1639#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1640#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1641#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1642#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1643 1644typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1645{ 1646 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1647 ULONG ulReserved[2]; 1648}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1649 1650 1651/****************************************************************************/ 1652// Structures used by DAC1OuputControlTable 1653// DAC2OuputControlTable 1654// LVTMAOutputControlTable (Before DEC30) 1655// TMDSAOutputControlTable (Before DEC30) 1656/****************************************************************************/ 1657typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1658{ 1659 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1660 // When the display is LCD, in addition to above: 1661 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1662 // ATOM_LCD_SELFTEST_STOP 1663 1664 UCHAR aucPadding[3]; // padding to DWORD aligned 1665}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1666 1667#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1668 1669 1670#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1671#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1672 1673#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1674#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1675 1676#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1677#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1678 1679#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1680#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1681 1682#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1683#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1684 1685#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1686#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1687 1688#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1689#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1690 1691#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1692#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1693#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1694 1695 1696typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1697{ 1698 // Possible value of ucAction 1699 // ATOM_TRANSMITTER_ACTION_LCD_BLON 1700 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1701 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1702 // ATOM_TRANSMITTER_ACTION_POWER_ON 1703 // ATOM_TRANSMITTER_ACTION_POWER_OFF 1704 UCHAR ucAction; 1705 UCHAR ucBriLevel; 1706 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1707}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1708 1709 1710 1711/****************************************************************************/ 1712// Structures used by BlankCRTCTable 1713/****************************************************************************/ 1714typedef struct _BLANK_CRTC_PARAMETERS 1715{ 1716 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1717 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1718 USHORT usBlackColorRCr; 1719 USHORT usBlackColorGY; 1720 USHORT usBlackColorBCb; 1721}BLANK_CRTC_PARAMETERS; 1722#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1723 1724/****************************************************************************/ 1725// Structures used by EnableCRTCTable 1726// EnableCRTCMemReqTable 1727// UpdateCRTC_DoubleBufferRegistersTable 1728/****************************************************************************/ 1729typedef struct _ENABLE_CRTC_PARAMETERS 1730{ 1731 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1732 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1733 UCHAR ucPadding[2]; 1734}ENABLE_CRTC_PARAMETERS; 1735#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1736 1737/****************************************************************************/ 1738// Structures used by SetCRTC_OverScanTable 1739/****************************************************************************/ 1740typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1741{ 1742 USHORT usOverscanRight; // right 1743 USHORT usOverscanLeft; // left 1744 USHORT usOverscanBottom; // bottom 1745 USHORT usOverscanTop; // top 1746 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1747 UCHAR ucPadding[3]; 1748}SET_CRTC_OVERSCAN_PARAMETERS; 1749#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1750 1751/****************************************************************************/ 1752// Structures used by SetCRTC_ReplicationTable 1753/****************************************************************************/ 1754typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1755{ 1756 UCHAR ucH_Replication; // horizontal replication 1757 UCHAR ucV_Replication; // vertical replication 1758 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1759 UCHAR ucPadding; 1760}SET_CRTC_REPLICATION_PARAMETERS; 1761#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1762 1763/****************************************************************************/ 1764// Structures used by SelectCRTC_SourceTable 1765/****************************************************************************/ 1766typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1767{ 1768 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1769 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1770 UCHAR ucPadding[2]; 1771}SELECT_CRTC_SOURCE_PARAMETERS; 1772#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1773 1774typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1775{ 1776 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1777 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1778 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1779 UCHAR ucPadding; 1780}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1781 1782//ucEncoderID 1783//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1784//#define ASIC_INT_TV_ENCODER_ID 0x02 1785//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1786//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1787//#define ASIC_EXT_TV_ENCODER_ID 0x06 1788//#define ASIC_INT_DVO_ENCODER_ID 0x07 1789//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1790//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1791 1792//ucEncodeMode 1793//#define ATOM_ENCODER_MODE_DP 0 1794//#define ATOM_ENCODER_MODE_LVDS 1 1795//#define ATOM_ENCODER_MODE_DVI 2 1796//#define ATOM_ENCODER_MODE_HDMI 3 1797//#define ATOM_ENCODER_MODE_SDVO 4 1798//#define ATOM_ENCODER_MODE_TV 13 1799//#define ATOM_ENCODER_MODE_CV 14 1800//#define ATOM_ENCODER_MODE_CRT 15 1801 1802 1803typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1804{ 1805 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1806 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1807 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1808 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1809}SELECT_CRTC_SOURCE_PARAMETERS_V3; 1810 1811 1812/****************************************************************************/ 1813// Structures used by SetPixelClockTable 1814// GetPixelClockTable 1815/****************************************************************************/ 1816//Major revision=1., Minor revision=1 1817typedef struct _PIXEL_CLOCK_PARAMETERS 1818{ 1819 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1820 // 0 means disable PPLL 1821 USHORT usRefDiv; // Reference divider 1822 USHORT usFbDiv; // feedback divider 1823 UCHAR ucPostDiv; // post divider 1824 UCHAR ucFracFbDiv; // fractional feedback divider 1825 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1826 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1827 UCHAR ucCRTC; // Which CRTC uses this Ppll 1828 UCHAR ucPadding; 1829}PIXEL_CLOCK_PARAMETERS; 1830 1831//Major revision=1., Minor revision=2, add ucMiscIfno 1832//ucMiscInfo: 1833#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1834#define MISC_DEVICE_INDEX_MASK 0xF0 1835#define MISC_DEVICE_INDEX_SHIFT 4 1836 1837typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1838{ 1839 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1840 // 0 means disable PPLL 1841 USHORT usRefDiv; // Reference divider 1842 USHORT usFbDiv; // feedback divider 1843 UCHAR ucPostDiv; // post divider 1844 UCHAR ucFracFbDiv; // fractional feedback divider 1845 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1846 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1847 UCHAR ucCRTC; // Which CRTC uses this Ppll 1848 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1849}PIXEL_CLOCK_PARAMETERS_V2; 1850 1851//Major revision=1., Minor revision=3, structure/definition change 1852//ucEncoderMode: 1853//ATOM_ENCODER_MODE_DP 1854//ATOM_ENOCDER_MODE_LVDS 1855//ATOM_ENOCDER_MODE_DVI 1856//ATOM_ENOCDER_MODE_HDMI 1857//ATOM_ENOCDER_MODE_SDVO 1858//ATOM_ENCODER_MODE_TV 13 1859//ATOM_ENCODER_MODE_CV 14 1860//ATOM_ENCODER_MODE_CRT 15 1861 1862//ucDVOConfig 1863//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1864//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1865//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1866//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1867//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1868//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1869//#define DVO_ENCODER_CONFIG_24BIT 0x08 1870 1871//ucMiscInfo: also changed, see below 1872#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1873#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1874#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1875#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1876#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1877#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1878#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1879// V1.4 for RoadRunner 1880#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1881#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1882 1883 1884typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1885{ 1886 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1887 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1888 USHORT usRefDiv; // Reference divider 1889 USHORT usFbDiv; // feedback divider 1890 UCHAR ucPostDiv; // post divider 1891 UCHAR ucFracFbDiv; // fractional feedback divider 1892 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1893 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1894 union 1895 { 1896 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1897 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1898 }; 1899 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1900 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1901 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1902}PIXEL_CLOCK_PARAMETERS_V3; 1903 1904#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1905#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1906 1907 1908typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1909{ 1910 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1911 // drive the pixel clock. not used for DCPLL case. 1912 union{ 1913 UCHAR ucReserved; 1914 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1915 }; 1916 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1917 // 0 means disable PPLL/DCPLL. 1918 USHORT usFbDiv; // feedback divider integer part. 1919 UCHAR ucPostDiv; // post divider. 1920 UCHAR ucRefDiv; // Reference divider 1921 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1922 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1923 // indicate which graphic encoder will be used. 1924 UCHAR ucEncoderMode; // Encoder mode: 1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1926 // bit[1]= when VGA timing is used. 1927 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1928 // bit[4]= RefClock source for PPLL. 1929 // =0: XTLAIN( default mode ) 1930 // =1: other external clock source, which is pre-defined 1931 // by VBIOS depend on the feature required. 1932 // bit[7:5]: reserved. 1933 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1934 1935}PIXEL_CLOCK_PARAMETERS_V5; 1936 1937#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1938#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1939#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1940#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1941#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1942#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1943#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1944 1945typedef struct _CRTC_PIXEL_CLOCK_FREQ 1946{ 1947#if ATOM_BIG_ENDIAN 1948 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1949 // drive the pixel clock. not used for DCPLL case. 1950 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1951 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1952#else 1953 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1954 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1955 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1956 // drive the pixel clock. not used for DCPLL case. 1957#endif 1958}CRTC_PIXEL_CLOCK_FREQ; 1959 1960typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1961{ 1962 union{ 1963 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1964 ULONG ulDispEngClkFreq; // dispclk frequency 1965 }; 1966 USHORT usFbDiv; // feedback divider integer part. 1967 UCHAR ucPostDiv; // post divider. 1968 UCHAR ucRefDiv; // Reference divider 1969 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1970 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1971 // indicate which graphic encoder will be used. 1972 UCHAR ucEncoderMode; // Encoder mode: 1973 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1974 // bit[1]= when VGA timing is used. 1975 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1976 // bit[4]= RefClock source for PPLL. 1977 // =0: XTLAIN( default mode ) 1978 // =1: other external clock source, which is pre-defined 1979 // by VBIOS depend on the feature required. 1980 // bit[7:5]: reserved. 1981 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1982 1983}PIXEL_CLOCK_PARAMETERS_V6; 1984 1985#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1986#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1987#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1988#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1989#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1990#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1) 1991#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1992#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4) 1993#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1994#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1995#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1996#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 1997 1998typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1999{ 2000 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 2001}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 2002 2003typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 2004{ 2005 UCHAR ucStatus; 2006 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 2007 UCHAR ucReserved[2]; 2008}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 2009 2010typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 2011{ 2012 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 2013}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 2014 2015typedef struct _PIXEL_CLOCK_PARAMETERS_V7 2016{ 2017 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2018 2019 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2020 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 2021 // indicate which graphic encoder will be used. 2022 UCHAR ucEncoderMode; // Encoder mode: 2023 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk 2024 // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) 2025 // bit[5:4]= RefClock source for PPLL. 2026 // =0: XTLAIN( default mode ) 2027 // =1: pcie 2028 // =2: GENLK 2029 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 2030 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp 2031 UCHAR ucReserved[2]; 2032 ULONG ulReserved; 2033}PIXEL_CLOCK_PARAMETERS_V7; 2034 2035//ucMiscInfo 2036#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01 2037#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02 2038#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04 2039#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08 2040#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30 2041#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00 2042#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10 2043#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20 2044 2045//ucDeepColorRatio 2046#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2047#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2048#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2049#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2050 2051// SetDCEClockTable input parameter for DCE11.1 2052typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1 2053{ 2054 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz. 2055 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS 2056 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1 2057 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1 2058 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1 2059}SET_DCE_CLOCK_PARAMETERS_V1_1; 2060 2061 2062typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 2063{ 2064 SET_DCE_CLOCK_PARAMETERS_V1_1 asParam; 2065 ULONG ulReserved[2]; 2066}SET_DCE_CLOCK_PS_ALLOCATION_V1_1; 2067 2068//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag 2069#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01 2070#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 2071#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 2072 2073// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above 2074typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 2075{ 2076 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2077 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2078 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2079 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2080 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2081}SET_DCE_CLOCK_PARAMETERS_V2_1; 2082 2083//ucDCEClkType 2084#define DCE_CLOCK_TYPE_DISPCLK 0 2085#define DCE_CLOCK_TYPE_DPREFCLK 1 2086#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable 2087 2088//ucDCEClkFlag when ucDCEClkType == DPREFCLK 2089#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03 2090#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00 2091#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01 2092#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02 2093#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03 2094 2095//ucDCEClkFlag when ucDCEClkType == PIXCLK 2096#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 2097#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2098#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2099#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2100#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2101#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04 2102 2103typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 2104{ 2105 SET_DCE_CLOCK_PARAMETERS_V2_1 asParam; 2106 ULONG ulReserved[2]; 2107}SET_DCE_CLOCK_PS_ALLOCATION_V2_1; 2108 2109 2110 2111/****************************************************************************/ 2112// Structures used by AdjustDisplayPllTable 2113/****************************************************************************/ 2114typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 2115{ 2116 USHORT usPixelClock; 2117 UCHAR ucTransmitterID; 2118 UCHAR ucEncodeMode; 2119 union 2120 { 2121 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 2122 UCHAR ucConfig; //if none DVO, not defined yet 2123 }; 2124 UCHAR ucReserved[3]; 2125}ADJUST_DISPLAY_PLL_PARAMETERS; 2126 2127#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 2128#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 2129 2130typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 2131{ 2132 USHORT usPixelClock; // target pixel clock 2133 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 2134 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 2135 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 2136 UCHAR ucExtTransmitterID; // external encoder id. 2137 UCHAR ucReserved[2]; 2138}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 2139 2140// usDispPllConfig v1.2 for RoadRunner 2141#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 2142#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 2143#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 2144#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 2145#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 2146#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 2147#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 2148#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 2149#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 2150#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 2151 2152 2153typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 2154{ 2155 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 2156 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 2157 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 2158 UCHAR ucReserved[2]; 2159}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 2160 2161typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 2162{ 2163 union 2164 { 2165 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 2166 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 2167 }; 2168} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 2169 2170/****************************************************************************/ 2171// Structures used by EnableYUVTable 2172/****************************************************************************/ 2173typedef struct _ENABLE_YUV_PARAMETERS 2174{ 2175 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 2176 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 2177 UCHAR ucPadding[2]; 2178}ENABLE_YUV_PARAMETERS; 2179#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 2180 2181/****************************************************************************/ 2182// Structures used by GetMemoryClockTable 2183/****************************************************************************/ 2184typedef struct _GET_MEMORY_CLOCK_PARAMETERS 2185{ 2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 2187} GET_MEMORY_CLOCK_PARAMETERS; 2188#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 2189 2190/****************************************************************************/ 2191// Structures used by GetEngineClockTable 2192/****************************************************************************/ 2193typedef struct _GET_ENGINE_CLOCK_PARAMETERS 2194{ 2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 2196} GET_ENGINE_CLOCK_PARAMETERS; 2197#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 2198 2199/****************************************************************************/ 2200// Following Structures and constant may be obsolete 2201/****************************************************************************/ 2202//Maxium 8 bytes,the data read in will be placed in the parameter space. 2203//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 2204typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2205{ 2206 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2207 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 2208 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 2209 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 2210 UCHAR ucSlaveAddr; //Read from which slave 2211 UCHAR ucLineNumber; //Read from which HW assisted line 2212}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 2213#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2214 2215 2216#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 2217#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 2218#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 2219#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 2220#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 2221 2222typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2223{ 2224 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2225 USHORT usByteOffset; //Write to which byte 2226 //Upper portion of usByteOffset is Format of data 2227 //1bytePS+offsetPS 2228 //2bytesPS+offsetPS 2229 //blockID+offsetPS 2230 //blockID+offsetID 2231 //blockID+counterID+offsetID 2232 UCHAR ucData; //PS data1 2233 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 2234 UCHAR ucSlaveAddr; //Write to which slave 2235 UCHAR ucLineNumber; //Write from which HW assisted line 2236}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 2237 2238#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2239 2240typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 2241{ 2242 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2243 UCHAR ucSlaveAddr; //Write to which slave 2244 UCHAR ucLineNumber; //Write from which HW assisted line 2245}SET_UP_HW_I2C_DATA_PARAMETERS; 2246 2247/**************************************************************************/ 2248#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2249 2250 2251/****************************************************************************/ 2252// Structures used by PowerConnectorDetectionTable 2253/****************************************************************************/ 2254typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 2255{ 2256 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2257 UCHAR ucPwrBehaviorId; 2258 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2259}POWER_CONNECTOR_DETECTION_PARAMETERS; 2260 2261typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 2262{ 2263 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2264 UCHAR ucReserved; 2265 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2266 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2267}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 2268 2269 2270/****************************LVDS SS Command Table Definitions**********************/ 2271 2272/****************************************************************************/ 2273// Structures used by EnableSpreadSpectrumOnPPLLTable 2274/****************************************************************************/ 2275typedef struct _ENABLE_LVDS_SS_PARAMETERS 2276{ 2277 USHORT usSpreadSpectrumPercentage; 2278 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2279 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 2280 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2281 UCHAR ucPadding[3]; 2282}ENABLE_LVDS_SS_PARAMETERS; 2283 2284//ucTableFormatRevision=1,ucTableContentRevision=2 2285typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 2286{ 2287 USHORT usSpreadSpectrumPercentage; 2288 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2289 UCHAR ucSpreadSpectrumStep; // 2290 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2291 UCHAR ucSpreadSpectrumDelay; 2292 UCHAR ucSpreadSpectrumRange; 2293 UCHAR ucPadding; 2294}ENABLE_LVDS_SS_PARAMETERS_V2; 2295 2296//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 2297typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 2298{ 2299 USHORT usSpreadSpectrumPercentage; 2300 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2301 UCHAR ucSpreadSpectrumStep; // 2302 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2303 UCHAR ucSpreadSpectrumDelay; 2304 UCHAR ucSpreadSpectrumRange; 2305 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 2306}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 2307 2308 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 2309{ 2310 USHORT usSpreadSpectrumPercentage; 2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2312 // Bit[1]: 1-Ext. 0-Int. 2313 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2314 // Bits[7:4] reserved 2315 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2316 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2317 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2318}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 2319 2320#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 2321#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 2322#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 2323#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 2324#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 2325#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 2326#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 2327#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2328#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2329#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2330#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2331 2332// Used by DCE5.0 2333 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2334{ 2335 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2337 // Bit[1]: 1-Ext. 0-Int. 2338 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2339 // Bits[7:4] reserved 2340 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2341 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2342 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2343}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2344 2345 2346#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2347#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2348#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2349#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2350#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2351#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2352#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2353#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2354#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2355#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2356#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2357#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2358 2359#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2360 2361typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2362{ 2363 PIXEL_CLOCK_PARAMETERS sPCLKInput; 2364 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2365}SET_PIXEL_CLOCK_PS_ALLOCATION; 2366 2367 2368 2369#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2370 2371/****************************************************************************/ 2372// Structures used by ### 2373/****************************************************************************/ 2374typedef struct _MEMORY_TRAINING_PARAMETERS 2375{ 2376 ULONG ulTargetMemoryClock; //In 10Khz unit 2377}MEMORY_TRAINING_PARAMETERS; 2378#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2379 2380 2381typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2382{ 2383 USHORT usMemTrainingMode; 2384 USHORT usReserved; 2385}MEMORY_TRAINING_PARAMETERS_V1_2; 2386 2387//usMemTrainingMode 2388#define NORMAL_MEMORY_TRAINING_MODE 0 2389#define ENTER_DRAM_SELFREFRESH_MODE 1 2390#define EXIT_DRAM_SELFRESH_MODE 2 2391 2392/****************************LVDS and other encoder command table definitions **********************/ 2393 2394 2395/****************************************************************************/ 2396// Structures used by LVDSEncoderControlTable (Before DEC30) 2397// LVTMAEncoderControlTable (Before DEC30) 2398// TMDSAEncoderControlTable (Before DEC30) 2399/****************************************************************************/ 2400typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2401{ 2402 USHORT usPixelClock; // in 10KHz; for bios convenient 2403 UCHAR ucMisc; // bit0=0: Enable single link 2404 // =1: Enable dual link 2405 // Bit1=0: 666RGB 2406 // =1: 888RGB 2407 UCHAR ucAction; // 0: turn off encoder 2408 // 1: setup and turn on encoder 2409}LVDS_ENCODER_CONTROL_PARAMETERS; 2410 2411#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2412 2413#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2414#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2415 2416#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2417#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2418 2419//ucTableFormatRevision=1,ucTableContentRevision=2 2420typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2421{ 2422 USHORT usPixelClock; // in 10KHz; for bios convenient 2423 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2424 UCHAR ucAction; // 0: turn off encoder 2425 // 1: setup and turn on encoder 2426 UCHAR ucTruncate; // bit0=0: Disable truncate 2427 // =1: Enable truncate 2428 // bit4=0: 666RGB 2429 // =1: 888RGB 2430 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2431 // =1: Enable spatial dithering 2432 // bit4=0: 666RGB 2433 // =1: 888RGB 2434 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2435 // =1: Enable temporal dithering 2436 // bit4=0: 666RGB 2437 // =1: 888RGB 2438 // bit5=0: Gray level 2 2439 // =1: Gray level 4 2440 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2441 // =1: 25FRC_SEL pattern F 2442 // bit6:5=0: 50FRC_SEL pattern A 2443 // =1: 50FRC_SEL pattern B 2444 // =2: 50FRC_SEL pattern C 2445 // =3: 50FRC_SEL pattern D 2446 // bit7=0: 75FRC_SEL pattern E 2447 // =1: 75FRC_SEL pattern F 2448}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2449 2450#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2451 2452#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2453#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2454 2455#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2456#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2457 2458 2459#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2460#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2461 2462#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2463#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2464 2465#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2466#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2467 2468/****************************************************************************/ 2469// Structures used by ### 2470/****************************************************************************/ 2471typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2472{ 2473 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2474 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2475 UCHAR ucPadding[2]; 2476}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2477 2478typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2479{ 2480 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2481 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2482}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2483 2484#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2485typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2486{ 2487 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2488 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2489}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2490 2491typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2492{ 2493 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2494 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2495}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2496 2497/****************************************************************************/ 2498// Structures used by DVOEncoderControlTable 2499/****************************************************************************/ 2500//ucTableFormatRevision=1,ucTableContentRevision=3 2501//ucDVOConfig: 2502#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2503#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2504#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2505#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2506#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2507#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2508#define DVO_ENCODER_CONFIG_24BIT 0x08 2509 2510typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2511{ 2512 USHORT usPixelClock; 2513 UCHAR ucDVOConfig; 2514 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2515 UCHAR ucReseved[4]; 2516}DVO_ENCODER_CONTROL_PARAMETERS_V3; 2517#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2518 2519typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2520{ 2521 USHORT usPixelClock; 2522 UCHAR ucDVOConfig; 2523 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2524 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2525 UCHAR ucReseved[3]; 2526}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2527#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2528 2529 2530//ucTableFormatRevision=1 2531//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2532// bit1=0: non-coherent mode 2533// =1: coherent mode 2534 2535//========================================================================================== 2536//Only change is here next time when changing encoder parameter definitions again! 2537#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2538#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2539 2540#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2541#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2542 2543#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2544#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2545 2546#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2547#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2548 2549//========================================================================================== 2550#define PANEL_ENCODER_MISC_DUAL 0x01 2551#define PANEL_ENCODER_MISC_COHERENT 0x02 2552#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2553#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2554 2555#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2556#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2557#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2558 2559#define PANEL_ENCODER_TRUNCATE_EN 0x01 2560#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2561#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2562#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2563#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2564#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2565#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2566#define PANEL_ENCODER_25FRC_MASK 0x10 2567#define PANEL_ENCODER_25FRC_E 0x00 2568#define PANEL_ENCODER_25FRC_F 0x10 2569#define PANEL_ENCODER_50FRC_MASK 0x60 2570#define PANEL_ENCODER_50FRC_A 0x00 2571#define PANEL_ENCODER_50FRC_B 0x20 2572#define PANEL_ENCODER_50FRC_C 0x40 2573#define PANEL_ENCODER_50FRC_D 0x60 2574#define PANEL_ENCODER_75FRC_MASK 0x80 2575#define PANEL_ENCODER_75FRC_E 0x00 2576#define PANEL_ENCODER_75FRC_F 0x80 2577 2578/****************************************************************************/ 2579// Structures used by SetVoltageTable 2580/****************************************************************************/ 2581#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2582#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2583#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2584#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2585#define SET_VOLTAGE_INIT_MODE 5 2586#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2587 2588#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2589#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2590#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2591 2592#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2593#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2594#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2595 2596typedef struct _SET_VOLTAGE_PARAMETERS 2597{ 2598 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2599 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2600 UCHAR ucVoltageIndex; // An index to tell which voltage level 2601 UCHAR ucReserved; 2602}SET_VOLTAGE_PARAMETERS; 2603 2604typedef struct _SET_VOLTAGE_PARAMETERS_V2 2605{ 2606 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2607 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2608 USHORT usVoltageLevel; // real voltage level 2609}SET_VOLTAGE_PARAMETERS_V2; 2610 2611// used by both SetVoltageTable v1.3 and v1.4 2612typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2613{ 2614 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2615 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2616 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2617}SET_VOLTAGE_PARAMETERS_V1_3; 2618 2619//ucVoltageType 2620#define VOLTAGE_TYPE_VDDC 1 2621#define VOLTAGE_TYPE_MVDDC 2 2622#define VOLTAGE_TYPE_MVDDQ 3 2623#define VOLTAGE_TYPE_VDDCI 4 2624#define VOLTAGE_TYPE_VDDGFX 5 2625#define VOLTAGE_TYPE_PCC 6 2626#define VOLTAGE_TYPE_MVPP 7 2627#define VOLTAGE_TYPE_LEDDPM 8 2628#define VOLTAGE_TYPE_PCC_MVDD 9 2629#define VOLTAGE_TYPE_PCIE_VDDC 10 2630#define VOLTAGE_TYPE_PCIE_VDDR 11 2631 2632#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2633#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2634#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2635#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2636#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2637#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2638#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2639#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2640#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2641#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2642 2643//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2644#define ATOM_SET_VOLTAGE 0 //Set voltage Level 2645#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2646#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2647#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2648#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2649#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2650 2651// define vitual voltage id in usVoltageLevel 2652#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2653#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2654#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2655#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2656#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2657#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2658#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2659#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2660 2661typedef struct _SET_VOLTAGE_PS_ALLOCATION 2662{ 2663 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2664 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2665}SET_VOLTAGE_PS_ALLOCATION; 2666 2667// New Added from SI for GetVoltageInfoTable, input parameter structure 2668typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2669{ 2670 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2671 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2672 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2673 ULONG ulReserved; 2674}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2675 2676// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2677typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2678{ 2679 ULONG ulVotlageGpioState; 2680 ULONG ulVoltageGPioMask; 2681}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2682 2683// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2684typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2685{ 2686 USHORT usVoltageLevel; 2687 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2688 ULONG ulReseved; 2689}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2690 2691// GetVoltageInfo v1.1 ucVoltageMode 2692#define ATOM_GET_VOLTAGE_VID 0x00 2693#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2694#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2695#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2696 2697// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2698#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2699// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2700#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2701 2702#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2703#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2704 2705 2706// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2707typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2708{ 2709 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2710 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2711 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2712 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2713}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2714 2715// New in GetVoltageInfo v1.2 ucVoltageMode 2716#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2717 2718// New Added from CI Hawaii for EVV feature 2719typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2720{ 2721 USHORT usVoltageLevel; // real voltage level in unit of mv 2722 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2723 USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2724 USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2725}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2726 2727 2728// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2729typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 2730{ 2731 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2732 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2733 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2734 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2735 ULONG ulReserved[3]; 2736}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; 2737 2738// New Added from CI Hawaii for EVV feature 2739typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 2740{ 2741 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv 2742 ULONG ulReserved[4]; 2743}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; 2744 2745 2746/****************************************************************************/ 2747// Structures used by GetSMUClockInfo 2748/****************************************************************************/ 2749typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 2750{ 2751 ULONG ulDfsPllOutputFreq:24; 2752 ULONG ucDfsDivider:8; 2753}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; 2754 2755typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 2756{ 2757 ULONG ulDfsOutputFreq; 2758}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; 2759 2760/****************************************************************************/ 2761// Structures used by TVEncoderControlTable 2762/****************************************************************************/ 2763typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2764{ 2765 USHORT usPixelClock; // in 10KHz; for bios convenient 2766 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2767 UCHAR ucAction; // 0: turn off encoder 2768 // 1: setup and turn on encoder 2769}TV_ENCODER_CONTROL_PARAMETERS; 2770 2771typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2772{ 2773 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2774 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2775}TV_ENCODER_CONTROL_PS_ALLOCATION; 2776 2777//==============================Data Table Portion==================================== 2778 2779 2780/****************************************************************************/ 2781// Structure used in Data.mtb 2782/****************************************************************************/ 2783typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2784{ 2785 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2786 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2787 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2788 USHORT StandardVESA_Timing; // Only used by Bios 2789 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2790 USHORT PaletteData; // Only used by BIOS 2791 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2792 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2793 USHORT SMU_Info; // Shared by various SW components,latest version 1.1 2794 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2795 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2796 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2797 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2798 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2799 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600 2800 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2801 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2802 USHORT SaveRestoreInfo; // Only used by Bios 2803 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2804 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2805 USHORT XTMDS_Info; // Will be obsolete from R600 2806 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2807 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2808 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2809 USHORT MC_InitParameter; // Only used by command table 2810 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2811 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2812 USHORT TV_VideoMode; // Only used by command table 2813 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2814 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2815 USHORT IntegratedSystemInfo; // Shared by various SW components 2816 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2817 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2818 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2819 USHORT ServiceInfo; 2820}ATOM_MASTER_LIST_OF_DATA_TABLES; 2821 2822typedef struct _ATOM_MASTER_DATA_TABLE 2823{ 2824 ATOM_COMMON_TABLE_HEADER sHeader; 2825 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2826}ATOM_MASTER_DATA_TABLE; 2827 2828// For backward compatible 2829#define LVDS_Info LCD_Info 2830#define DAC_Info PaletteData 2831#define TMDS_Info DIGTransmitterInfo 2832#define CompassionateData GPUVirtualizationInfo 2833#define AnalogTV_Info SMU_Info 2834#define ComponentVideoInfo GFX_Info 2835 2836/****************************************************************************/ 2837// Structure used in MultimediaCapabilityInfoTable 2838/****************************************************************************/ 2839typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2840{ 2841 ATOM_COMMON_TABLE_HEADER sHeader; 2842 ULONG ulSignature; // HW info table signature string "$ATI" 2843 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2844 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2845 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2846 UCHAR ucHostPortInfo; // Provides host port configuration information 2847}ATOM_MULTIMEDIA_CAPABILITY_INFO; 2848 2849 2850/****************************************************************************/ 2851// Structure used in MultimediaConfigInfoTable 2852/****************************************************************************/ 2853typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2854{ 2855 ATOM_COMMON_TABLE_HEADER sHeader; 2856 ULONG ulSignature; // MM info table signature sting "$MMT" 2857 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2858 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2859 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2860 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2861 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2862 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2863 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2864 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2865 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2866 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2867 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2868 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2869}ATOM_MULTIMEDIA_CONFIG_INFO; 2870 2871 2872/****************************************************************************/ 2873// Structures used in FirmwareInfoTable 2874/****************************************************************************/ 2875 2876// usBIOSCapability Defintion: 2877// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2878// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2879// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2880// Others: Reserved 2881#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2882#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2883#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2884#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2885#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2886#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2887#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2888#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2889#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2890#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2891#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2892#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2893#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2894#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2895 2896 2897#ifndef _H2INC 2898 2899//Please don't add or expand this bitfield structure below, this one will retire soon.! 2900typedef struct _ATOM_FIRMWARE_CAPABILITY 2901{ 2902#if ATOM_BIG_ENDIAN 2903 USHORT Reserved:1; 2904 USHORT SCL2Redefined:1; 2905 USHORT PostWithoutModeSet:1; 2906 USHORT HyperMemory_Size:4; 2907 USHORT HyperMemory_Support:1; 2908 USHORT PPMode_Assigned:1; 2909 USHORT WMI_SUPPORT:1; 2910 USHORT GPUControlsBL:1; 2911 USHORT EngineClockSS_Support:1; 2912 USHORT MemoryClockSS_Support:1; 2913 USHORT ExtendedDesktopSupport:1; 2914 USHORT DualCRTC_Support:1; 2915 USHORT FirmwarePosted:1; 2916#else 2917 USHORT FirmwarePosted:1; 2918 USHORT DualCRTC_Support:1; 2919 USHORT ExtendedDesktopSupport:1; 2920 USHORT MemoryClockSS_Support:1; 2921 USHORT EngineClockSS_Support:1; 2922 USHORT GPUControlsBL:1; 2923 USHORT WMI_SUPPORT:1; 2924 USHORT PPMode_Assigned:1; 2925 USHORT HyperMemory_Support:1; 2926 USHORT HyperMemory_Size:4; 2927 USHORT PostWithoutModeSet:1; 2928 USHORT SCL2Redefined:1; 2929 USHORT Reserved:1; 2930#endif 2931}ATOM_FIRMWARE_CAPABILITY; 2932 2933typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2934{ 2935 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2936 USHORT susAccess; 2937}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2938 2939#else 2940 2941typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2942{ 2943 USHORT susAccess; 2944}ATOM_FIRMWARE_CAPABILITY_ACCESS; 2945 2946#endif 2947 2948typedef struct _ATOM_FIRMWARE_INFO 2949{ 2950 ATOM_COMMON_TABLE_HEADER sHeader; 2951 ULONG ulFirmwareRevision; 2952 ULONG ulDefaultEngineClock; //In 10Khz unit 2953 ULONG ulDefaultMemoryClock; //In 10Khz unit 2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2959 ULONG ulASICMaxEngineClock; //In 10Khz unit 2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2961 UCHAR ucASICMaxTemperature; 2962 UCHAR ucPadding[3]; //Don't use them 2963 ULONG aulReservedForBIOS[3]; //Don't use them 2964 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2965 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2966 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2967 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2968 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2969 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2970 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2971 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2972 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2973 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2974 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2975 USHORT usReferenceClock; //In 10Khz unit 2976 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2977 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2978 UCHAR ucDesign_ID; //Indicate what is the board design 2979 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2980}ATOM_FIRMWARE_INFO; 2981 2982typedef struct _ATOM_FIRMWARE_INFO_V1_2 2983{ 2984 ATOM_COMMON_TABLE_HEADER sHeader; 2985 ULONG ulFirmwareRevision; 2986 ULONG ulDefaultEngineClock; //In 10Khz unit 2987 ULONG ulDefaultMemoryClock; //In 10Khz unit 2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2993 ULONG ulASICMaxEngineClock; //In 10Khz unit 2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2995 UCHAR ucASICMaxTemperature; 2996 UCHAR ucMinAllowedBL_Level; 2997 UCHAR ucPadding[2]; //Don't use them 2998 ULONG aulReservedForBIOS[2]; //Don't use them 2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3000 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3001 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3002 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3003 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3004 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3005 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3006 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3007 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3008 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3009 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3010 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3011 USHORT usReferenceClock; //In 10Khz unit 3012 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3013 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3014 UCHAR ucDesign_ID; //Indicate what is the board design 3015 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3016}ATOM_FIRMWARE_INFO_V1_2; 3017 3018typedef struct _ATOM_FIRMWARE_INFO_V1_3 3019{ 3020 ATOM_COMMON_TABLE_HEADER sHeader; 3021 ULONG ulFirmwareRevision; 3022 ULONG ulDefaultEngineClock; //In 10Khz unit 3023 ULONG ulDefaultMemoryClock; //In 10Khz unit 3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3029 ULONG ulASICMaxEngineClock; //In 10Khz unit 3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3031 UCHAR ucASICMaxTemperature; 3032 UCHAR ucMinAllowedBL_Level; 3033 UCHAR ucPadding[2]; //Don't use them 3034 ULONG aulReservedForBIOS; //Don't use them 3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3037 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3038 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3039 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3040 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3041 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3042 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3043 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3044 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3045 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3046 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3047 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3048 USHORT usReferenceClock; //In 10Khz unit 3049 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3050 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3051 UCHAR ucDesign_ID; //Indicate what is the board design 3052 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3053}ATOM_FIRMWARE_INFO_V1_3; 3054 3055typedef struct _ATOM_FIRMWARE_INFO_V1_4 3056{ 3057 ATOM_COMMON_TABLE_HEADER sHeader; 3058 ULONG ulFirmwareRevision; 3059 ULONG ulDefaultEngineClock; //In 10Khz unit 3060 ULONG ulDefaultMemoryClock; //In 10Khz unit 3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3066 ULONG ulASICMaxEngineClock; //In 10Khz unit 3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3068 UCHAR ucASICMaxTemperature; 3069 UCHAR ucMinAllowedBL_Level; 3070 USHORT usBootUpVDDCVoltage; //In MV unit 3071 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3072 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3075 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3076 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3077 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3078 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3079 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3080 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3081 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3082 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3083 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3084 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3085 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3086 USHORT usReferenceClock; //In 10Khz unit 3087 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3088 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3089 UCHAR ucDesign_ID; //Indicate what is the board design 3090 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3091}ATOM_FIRMWARE_INFO_V1_4; 3092 3093//the structure below to be used from Cypress 3094typedef struct _ATOM_FIRMWARE_INFO_V2_1 3095{ 3096 ATOM_COMMON_TABLE_HEADER sHeader; 3097 ULONG ulFirmwareRevision; 3098 ULONG ulDefaultEngineClock; //In 10Khz unit 3099 ULONG ulDefaultMemoryClock; //In 10Khz unit 3100 ULONG ulReserved1; 3101 ULONG ulReserved2; 3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3105 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 3107 UCHAR ucReserved1; //Was ucASICMaxTemperature; 3108 UCHAR ucMinAllowedBL_Level; 3109 USHORT usBootUpVDDCVoltage; //In MV unit 3110 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3111 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3112 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3114 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3115 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3116 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3117 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3118 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3119 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3120 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3121 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3122 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3123 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3124 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3125 USHORT usCoreReferenceClock; //In 10Khz unit 3126 USHORT usMemoryReferenceClock; //In 10Khz unit 3127 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3128 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3129 UCHAR ucReserved4[3]; 3130 3131}ATOM_FIRMWARE_INFO_V2_1; 3132 3133//the structure below to be used from NI 3134//ucTableFormatRevision=2 3135//ucTableContentRevision=2 3136 3137typedef struct _PRODUCT_BRANDING 3138{ 3139 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 3140 UCHAR ucReserved:2; // Bit[3:2] Reserved 3141 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 3142}PRODUCT_BRANDING; 3143 3144typedef struct _ATOM_FIRMWARE_INFO_V2_2 3145{ 3146 ATOM_COMMON_TABLE_HEADER sHeader; 3147 ULONG ulFirmwareRevision; 3148 ULONG ulDefaultEngineClock; //In 10Khz unit 3149 ULONG ulDefaultMemoryClock; //In 10Khz unit 3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit 3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 3152 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 3153 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3155 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 3156 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 3157 UCHAR ucReserved3; //Was ucASICMaxTemperature; 3158 UCHAR ucMinAllowedBL_Level; 3159 USHORT usBootUpVDDCVoltage; //In MV unit 3160 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3161 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3162 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3164 UCHAR ucRemoteDisplayConfig; 3165 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 3166 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 3167 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 3168 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 3169 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3170 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3171 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3172 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3173 USHORT usCoreReferenceClock; //In 10Khz unit 3174 USHORT usMemoryReferenceClock; //In 10Khz unit 3175 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3176 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3177 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 3178 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 3179 UCHAR ucReserved9; 3180 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3181 USHORT usBootUpVDDGFXVoltage; //In unit of mv; 3182 ULONG ulReserved10[3]; // New added comparing to previous version 3183}ATOM_FIRMWARE_INFO_V2_2; 3184 3185#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 3186 3187 3188// definition of ucRemoteDisplayConfig 3189#define REMOTE_DISPLAY_DISABLE 0x00 3190#define REMOTE_DISPLAY_ENABLE 0x01 3191 3192/****************************************************************************/ 3193// Structures used in IntegratedSystemInfoTable 3194/****************************************************************************/ 3195#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 3196#define IGP_CAP_FLAG_AC_CARD 0x4 3197#define IGP_CAP_FLAG_SDVO_CARD 0x8 3198#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 3199 3200typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 3201{ 3202 ATOM_COMMON_TABLE_HEADER sHeader; 3203 ULONG ulBootUpEngineClock; //in 10kHz unit 3204 ULONG ulBootUpMemoryClock; //in 10kHz unit 3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit 3207 UCHAR ucNumberOfCyclesInPeriodHi; 3208 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 3209 USHORT usReserved1; 3210 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 3211 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 3212 ULONG ulReserved[2]; 3213 3214 USHORT usFSBClock; //In MHz unit 3215 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 3216 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode 3218 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 3219 USHORT usK8MemoryClock; //in MHz unit 3220 USHORT usK8SyncStartDelay; //in 0.01 us unit 3221 USHORT usK8DataReturnTime; //in 0.01 us unit 3222 UCHAR ucMaxNBVoltage; 3223 UCHAR ucMinNBVoltage; 3224 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 3225 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 3226 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 3227 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 3228 UCHAR ucMaxNBVoltageHigh; 3229 UCHAR ucMinNBVoltageHigh; 3230}ATOM_INTEGRATED_SYSTEM_INFO; 3231 3232/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 3233ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 3234 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 3235ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3236 For AMD IGP,for now this can be 0 3237ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3238 For AMD IGP,for now this can be 0 3239 3240usFSBClock: For Intel IGP,it's FSB Freq 3241 For AMD IGP,it's HT Link Speed 3242 3243usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 3244usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3245usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3246 3247VC:Voltage Control 3248ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3249ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3250 3251ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 3252ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 3253 3254ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3255ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3256 3257 3258usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 3259usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 3260*/ 3261 3262 3263/* 3264The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 3265Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 3266The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 3267 3268SW components can access the IGP system infor structure in the same way as before 3269*/ 3270 3271 3272typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 3273{ 3274 ATOM_COMMON_TABLE_HEADER sHeader; 3275 ULONG ulBootUpEngineClock; //in 10kHz unit 3276 ULONG ulReserved1[2]; //must be 0x0 for the reserved 3277 ULONG ulBootUpUMAClock; //in 10kHz unit 3278 ULONG ulBootUpSidePortClock; //in 10kHz unit 3279 ULONG ulMinSidePortClock; //in 10kHz unit 3280 ULONG ulReserved2[6]; //must be 0x0 for the reserved 3281 ULONG ulSystemConfig; //see explanation below 3282 ULONG ulBootUpReqDisplayVector; 3283 ULONG ulOtherDisplayMisc; 3284 ULONG ulDDISlot1Config; 3285 ULONG ulDDISlot2Config; 3286 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3287 UCHAR ucUMAChannelNumber; 3288 UCHAR ucDockingPinBit; 3289 UCHAR ucDockingPinPolarity; 3290 ULONG ulDockingPinCFGInfo; 3291 ULONG ulCPUCapInfo; 3292 USHORT usNumberOfCyclesInPeriod; 3293 USHORT usMaxNBVoltage; 3294 USHORT usMinNBVoltage; 3295 USHORT usBootUpNBVoltage; 3296 ULONG ulHTLinkFreq; //in 10Khz 3297 USHORT usMinHTLinkWidth; 3298 USHORT usMaxHTLinkWidth; 3299 USHORT usUMASyncStartDelay; 3300 USHORT usUMADataReturnTime; 3301 USHORT usLinkStatusZeroTime; 3302 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 3305 USHORT usMaxUpStreamHTLinkWidth; 3306 USHORT usMaxDownStreamHTLinkWidth; 3307 USHORT usMinUpStreamHTLinkWidth; 3308 USHORT usMinDownStreamHTLinkWidth; 3309 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 3310 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 3311 ULONG ulReserved3[96]; //must be 0x0 3312}ATOM_INTEGRATED_SYSTEM_INFO_V2; 3313 3314/* 3315ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 3316ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 3317ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 3318 3319ulSystemConfig: 3320Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 3321Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 3322 =0: system boots up at driver control state. Power state depends on PowerPlay table. 3323Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 3324Bit[3]=1: Only one power state(Performance) will be supported. 3325 =0: Multiple power states supported from PowerPlay table. 3326Bit[4]=1: CLMC is supported and enabled on current system. 3327 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 3328Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 3329 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 3330Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 3331 =0: Voltage settings is determined by powerplay table. 3332Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 3333 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 3334Bit[8]=1: CDLF is supported and enabled on current system. 3335 =0: CDLF is not supported or enabled on current system. 3336Bit[9]=1: DLL Shut Down feature is enabled on current system. 3337 =0: DLL Shut Down feature is not enabled or supported on current system. 3338 3339ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 3340 3341ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 3342 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 3343 3344ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 3345 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 3346 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 3347 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 3348 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 3349 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 3350 3351 [15:8] - Lane configuration attribute; 3352 [23:16]- Connector type, possible value: 3353 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 3354 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 3355 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 3356 CONNECTOR_OBJECT_ID_DISPLAYPORT 3357 CONNECTOR_OBJECT_ID_eDP 3358 [31:24]- Reserved 3359 3360ulDDISlot2Config: Same as Slot1. 3361ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 3362For IGP, Hypermemory is the only memory type showed in CCC. 3363 3364ucUMAChannelNumber: how many channels for the UMA; 3365 3366ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 3367ucDockingPinBit: which bit in this register to read the pin status; 3368ucDockingPinPolarity:Polarity of the pin when docked; 3369 3370ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3371 3372usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3373 3374usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3375usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3376 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3377 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3378 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3379 3380usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3381 3382 3383ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3384usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3385 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3386usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3387 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3388 3389usUMASyncStartDelay: Memory access latency, required for watermark calculation 3390usUMADataReturnTime: Memory access latency, required for watermark calculation 3391usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3392for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3393 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3394 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3395 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3396 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3397 3398ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3399 This must be less than or equal to ulHTLinkFreq(bootup frequency). 3400ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3401 This must be less than or equal to ulHighVoltageHTLinkFreq. 3402 3403usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3404usMaxDownStreamHTLinkWidth: same as above. 3405usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3406usMinDownStreamHTLinkWidth: same as above. 3407*/ 3408 3409// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3410#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3411#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3412#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3413#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3414#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3415#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3416 3417#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3418 3419#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3420#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3421#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3422#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3423#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3424#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3425#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3426#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3427#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3428#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3429 3430#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3431 3432#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3433#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3434#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3435#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3436#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3437#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3438 3439#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3440#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3441#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3442 3443#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3444 3445// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3446typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3447{ 3448 ATOM_COMMON_TABLE_HEADER sHeader; 3449 ULONG ulBootUpEngineClock; //in 10kHz unit 3450 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3451 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3452 ULONG ulBootUpUMAClock; //in 10kHz unit 3453 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3454 ULONG ulBootUpReqDisplayVector; 3455 ULONG ulOtherDisplayMisc; 3456 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3457 ULONG ulSystemConfig; //TBD 3458 ULONG ulCPUCapInfo; //TBD 3459 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3460 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3461 USHORT usBootUpNBVoltage; //boot up NB voltage 3462 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3463 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3464 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3465 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3466 ULONG ulDDISlot2Config; 3467 ULONG ulDDISlot3Config; 3468 ULONG ulDDISlot4Config; 3469 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3470 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3471 UCHAR ucUMAChannelNumber; 3472 USHORT usReserved; 3473 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3474 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3475 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3476 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3477 ULONG ulReserved6[61]; //must be 0x0 3478}ATOM_INTEGRATED_SYSTEM_INFO_V5; 3479 3480 3481 3482/****************************************************************************/ 3483// Structure used in GPUVirtualizationInfoTable 3484/****************************************************************************/ 3485typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3486{ 3487 ATOM_COMMON_TABLE_HEADER sHeader; 3488 ULONG ulMCUcodeRomStartAddr; 3489 ULONG ulMCUcodeLength; 3490 ULONG ulSMCUcodeRomStartAddr; 3491 ULONG ulSMCUcodeLength; 3492 ULONG ulRLCVUcodeRomStartAddr; 3493 ULONG ulRLCVUcodeLength; 3494 ULONG ulTOCUcodeStartAddr; 3495 ULONG ulTOCUcodeLength; 3496 ULONG ulSMCPatchTableStartAddr; 3497 ULONG ulSmcPatchTableLength; 3498 ULONG ulSystemFlag; 3499}ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3500 3501 3502#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3503#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3504#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3505#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3506#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3507#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3508#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3509#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3510#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3511#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3512#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3513#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3514#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3515#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3516 3517// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3518#define ASIC_INT_DAC1_ENCODER_ID 0x00 3519#define ASIC_INT_TV_ENCODER_ID 0x02 3520#define ASIC_INT_DIG1_ENCODER_ID 0x03 3521#define ASIC_INT_DAC2_ENCODER_ID 0x04 3522#define ASIC_EXT_TV_ENCODER_ID 0x06 3523#define ASIC_INT_DVO_ENCODER_ID 0x07 3524#define ASIC_INT_DIG2_ENCODER_ID 0x09 3525#define ASIC_EXT_DIG_ENCODER_ID 0x05 3526#define ASIC_EXT_DIG2_ENCODER_ID 0x08 3527#define ASIC_INT_DIG3_ENCODER_ID 0x0a 3528#define ASIC_INT_DIG4_ENCODER_ID 0x0b 3529#define ASIC_INT_DIG5_ENCODER_ID 0x0c 3530#define ASIC_INT_DIG6_ENCODER_ID 0x0d 3531#define ASIC_INT_DIG7_ENCODER_ID 0x0e 3532 3533//define Encoder attribute 3534#define ATOM_ANALOG_ENCODER 0 3535#define ATOM_DIGITAL_ENCODER 1 3536#define ATOM_DP_ENCODER 2 3537 3538#define ATOM_ENCODER_ENUM_MASK 0x70 3539#define ATOM_ENCODER_ENUM_ID1 0x00 3540#define ATOM_ENCODER_ENUM_ID2 0x10 3541#define ATOM_ENCODER_ENUM_ID3 0x20 3542#define ATOM_ENCODER_ENUM_ID4 0x30 3543#define ATOM_ENCODER_ENUM_ID5 0x40 3544#define ATOM_ENCODER_ENUM_ID6 0x50 3545 3546#define ATOM_DEVICE_CRT1_INDEX 0x00000000 3547#define ATOM_DEVICE_LCD1_INDEX 0x00000001 3548#define ATOM_DEVICE_TV1_INDEX 0x00000002 3549#define ATOM_DEVICE_DFP1_INDEX 0x00000003 3550#define ATOM_DEVICE_CRT2_INDEX 0x00000004 3551#define ATOM_DEVICE_LCD2_INDEX 0x00000005 3552#define ATOM_DEVICE_DFP6_INDEX 0x00000006 3553#define ATOM_DEVICE_DFP2_INDEX 0x00000007 3554#define ATOM_DEVICE_CV_INDEX 0x00000008 3555#define ATOM_DEVICE_DFP3_INDEX 0x00000009 3556#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3557#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3558 3559#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3560#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3561#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3562#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3563#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3564#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3565#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3566 3567#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3568 3569#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3570#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3571#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3572#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3573#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3574#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3575#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3576#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3577#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3578#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3579#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3580#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3581 3582 3583#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3584#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3585#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3586#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3587 3588#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3589#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3590#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3591#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3592#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3593#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3594#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3595#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3596#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3597#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3598#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3599#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3600#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3601#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3602#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3603 3604 3605#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3606#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3607#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3608#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3609#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3610#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3611 3612#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3613 3614#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3615#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3616 3617#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3618#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3619#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3620#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3621#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3622#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3623 3624#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3625#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3626#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3627#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3628 3629// usDeviceSupport: 3630// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3631// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3632// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3633// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3634// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3635// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3636// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3637// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3638// Bit 8 = 0 - no CV support= 1- CV is supported 3639// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3640// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3641// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3642// 3643// 3644 3645/****************************************************************************/ 3646// Structure used in MclkSS_InfoTable 3647/****************************************************************************/ 3648// ucI2C_ConfigID 3649// [7:0] - I2C LINE Associate ID 3650// = 0 - no I2C 3651// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3652// = 0, [6:0]=SW assisted I2C ID 3653// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3654// = 2, HW engine for Multimedia use 3655// = 3-7 Reserved for future I2C engines 3656// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3657 3658typedef struct _ATOM_I2C_ID_CONFIG 3659{ 3660#if ATOM_BIG_ENDIAN 3661 UCHAR bfHW_Capable:1; 3662 UCHAR bfHW_EngineID:3; 3663 UCHAR bfI2C_LineMux:4; 3664#else 3665 UCHAR bfI2C_LineMux:4; 3666 UCHAR bfHW_EngineID:3; 3667 UCHAR bfHW_Capable:1; 3668#endif 3669}ATOM_I2C_ID_CONFIG; 3670 3671typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3672{ 3673 ATOM_I2C_ID_CONFIG sbfAccess; 3674 UCHAR ucAccess; 3675}ATOM_I2C_ID_CONFIG_ACCESS; 3676 3677 3678/****************************************************************************/ 3679// Structure used in GPIO_I2C_InfoTable 3680/****************************************************************************/ 3681typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3682{ 3683 USHORT usClkMaskRegisterIndex; 3684 USHORT usClkEnRegisterIndex; 3685 USHORT usClkY_RegisterIndex; 3686 USHORT usClkA_RegisterIndex; 3687 USHORT usDataMaskRegisterIndex; 3688 USHORT usDataEnRegisterIndex; 3689 USHORT usDataY_RegisterIndex; 3690 USHORT usDataA_RegisterIndex; 3691 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3692 UCHAR ucClkMaskShift; 3693 UCHAR ucClkEnShift; 3694 UCHAR ucClkY_Shift; 3695 UCHAR ucClkA_Shift; 3696 UCHAR ucDataMaskShift; 3697 UCHAR ucDataEnShift; 3698 UCHAR ucDataY_Shift; 3699 UCHAR ucDataA_Shift; 3700 UCHAR ucReserved1; 3701 UCHAR ucReserved2; 3702}ATOM_GPIO_I2C_ASSIGMENT; 3703 3704typedef struct _ATOM_GPIO_I2C_INFO 3705{ 3706 ATOM_COMMON_TABLE_HEADER sHeader; 3707 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3708}ATOM_GPIO_I2C_INFO; 3709 3710/****************************************************************************/ 3711// Common Structure used in other structures 3712/****************************************************************************/ 3713 3714#ifndef _H2INC 3715 3716//Please don't add or expand this bitfield structure below, this one will retire soon.! 3717typedef struct _ATOM_MODE_MISC_INFO 3718{ 3719#if ATOM_BIG_ENDIAN 3720 USHORT Reserved:6; 3721 USHORT RGB888:1; 3722 USHORT DoubleClock:1; 3723 USHORT Interlace:1; 3724 USHORT CompositeSync:1; 3725 USHORT V_ReplicationBy2:1; 3726 USHORT H_ReplicationBy2:1; 3727 USHORT VerticalCutOff:1; 3728 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3729 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3730 USHORT HorizontalCutOff:1; 3731#else 3732 USHORT HorizontalCutOff:1; 3733 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3734 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3735 USHORT VerticalCutOff:1; 3736 USHORT H_ReplicationBy2:1; 3737 USHORT V_ReplicationBy2:1; 3738 USHORT CompositeSync:1; 3739 USHORT Interlace:1; 3740 USHORT DoubleClock:1; 3741 USHORT RGB888:1; 3742 USHORT Reserved:6; 3743#endif 3744}ATOM_MODE_MISC_INFO; 3745 3746typedef union _ATOM_MODE_MISC_INFO_ACCESS 3747{ 3748 ATOM_MODE_MISC_INFO sbfAccess; 3749 USHORT usAccess; 3750}ATOM_MODE_MISC_INFO_ACCESS; 3751 3752#else 3753 3754typedef union _ATOM_MODE_MISC_INFO_ACCESS 3755{ 3756 USHORT usAccess; 3757}ATOM_MODE_MISC_INFO_ACCESS; 3758 3759#endif 3760 3761// usModeMiscInfo- 3762#define ATOM_H_CUTOFF 0x01 3763#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3764#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3765#define ATOM_V_CUTOFF 0x08 3766#define ATOM_H_REPLICATIONBY2 0x10 3767#define ATOM_V_REPLICATIONBY2 0x20 3768#define ATOM_COMPOSITESYNC 0x40 3769#define ATOM_INTERLACE 0x80 3770#define ATOM_DOUBLE_CLOCK_MODE 0x100 3771#define ATOM_RGB888_MODE 0x200 3772 3773//usRefreshRate- 3774#define ATOM_REFRESH_43 43 3775#define ATOM_REFRESH_47 47 3776#define ATOM_REFRESH_56 56 3777#define ATOM_REFRESH_60 60 3778#define ATOM_REFRESH_65 65 3779#define ATOM_REFRESH_70 70 3780#define ATOM_REFRESH_72 72 3781#define ATOM_REFRESH_75 75 3782#define ATOM_REFRESH_85 85 3783 3784// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3785// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3786// 3787// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3788// = EDID_HA + EDID_HBL 3789// VESA_HDISP = VESA_ACTIVE = EDID_HA 3790// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3791// = EDID_HA + EDID_HSO 3792// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3793// VESA_BORDER = EDID_BORDER 3794 3795 3796/****************************************************************************/ 3797// Structure used in SetCRTC_UsingDTDTimingTable 3798/****************************************************************************/ 3799typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3800{ 3801 USHORT usH_Size; 3802 USHORT usH_Blanking_Time; 3803 USHORT usV_Size; 3804 USHORT usV_Blanking_Time; 3805 USHORT usH_SyncOffset; 3806 USHORT usH_SyncWidth; 3807 USHORT usV_SyncOffset; 3808 USHORT usV_SyncWidth; 3809 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3810 UCHAR ucH_Border; // From DFP EDID 3811 UCHAR ucV_Border; 3812 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3813 UCHAR ucPadding[3]; 3814}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3815 3816/****************************************************************************/ 3817// Structure used in SetCRTC_TimingTable 3818/****************************************************************************/ 3819typedef struct _SET_CRTC_TIMING_PARAMETERS 3820{ 3821 USHORT usH_Total; // horizontal total 3822 USHORT usH_Disp; // horizontal display 3823 USHORT usH_SyncStart; // horozontal Sync start 3824 USHORT usH_SyncWidth; // horizontal Sync width 3825 USHORT usV_Total; // vertical total 3826 USHORT usV_Disp; // vertical display 3827 USHORT usV_SyncStart; // vertical Sync start 3828 USHORT usV_SyncWidth; // vertical Sync width 3829 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3830 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3831 UCHAR ucOverscanRight; // right 3832 UCHAR ucOverscanLeft; // left 3833 UCHAR ucOverscanBottom; // bottom 3834 UCHAR ucOverscanTop; // top 3835 UCHAR ucReserved; 3836}SET_CRTC_TIMING_PARAMETERS; 3837#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3838 3839 3840/****************************************************************************/ 3841// Structure used in StandardVESA_TimingTable 3842// AnalogTV_InfoTable 3843// ComponentVideoInfoTable 3844/****************************************************************************/ 3845typedef struct _ATOM_MODE_TIMING 3846{ 3847 USHORT usCRTC_H_Total; 3848 USHORT usCRTC_H_Disp; 3849 USHORT usCRTC_H_SyncStart; 3850 USHORT usCRTC_H_SyncWidth; 3851 USHORT usCRTC_V_Total; 3852 USHORT usCRTC_V_Disp; 3853 USHORT usCRTC_V_SyncStart; 3854 USHORT usCRTC_V_SyncWidth; 3855 USHORT usPixelClock; //in 10Khz unit 3856 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3857 USHORT usCRTC_OverscanRight; 3858 USHORT usCRTC_OverscanLeft; 3859 USHORT usCRTC_OverscanBottom; 3860 USHORT usCRTC_OverscanTop; 3861 USHORT usReserve; 3862 UCHAR ucInternalModeNumber; 3863 UCHAR ucRefreshRate; 3864}ATOM_MODE_TIMING; 3865 3866typedef struct _ATOM_DTD_FORMAT 3867{ 3868 USHORT usPixClk; 3869 USHORT usHActive; 3870 USHORT usHBlanking_Time; 3871 USHORT usVActive; 3872 USHORT usVBlanking_Time; 3873 USHORT usHSyncOffset; 3874 USHORT usHSyncWidth; 3875 USHORT usVSyncOffset; 3876 USHORT usVSyncWidth; 3877 USHORT usImageHSize; 3878 USHORT usImageVSize; 3879 UCHAR ucHBorder; 3880 UCHAR ucVBorder; 3881 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3882 UCHAR ucInternalModeNumber; 3883 UCHAR ucRefreshRate; 3884}ATOM_DTD_FORMAT; 3885 3886/****************************************************************************/ 3887// Structure used in LVDS_InfoTable 3888// * Need a document to describe this table 3889/****************************************************************************/ 3890#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3891#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3892#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3893#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3894#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3895 3896//ucTableFormatRevision=1 3897//ucTableContentRevision=1 3898typedef struct _ATOM_LVDS_INFO 3899{ 3900 ATOM_COMMON_TABLE_HEADER sHeader; 3901 ATOM_DTD_FORMAT sLCDTiming; 3902 USHORT usModePatchTableOffset; 3903 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3904 USHORT usOffDelayInMs; 3905 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3906 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3907 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3908 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3909 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3910 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3911 UCHAR ucPanelDefaultRefreshRate; 3912 UCHAR ucPanelIdentification; 3913 UCHAR ucSS_Id; 3914}ATOM_LVDS_INFO; 3915 3916//ucTableFormatRevision=1 3917//ucTableContentRevision=2 3918typedef struct _ATOM_LVDS_INFO_V12 3919{ 3920 ATOM_COMMON_TABLE_HEADER sHeader; 3921 ATOM_DTD_FORMAT sLCDTiming; 3922 USHORT usExtInfoTableOffset; 3923 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3924 USHORT usOffDelayInMs; 3925 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3926 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3927 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3928 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3929 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3930 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3931 UCHAR ucPanelDefaultRefreshRate; 3932 UCHAR ucPanelIdentification; 3933 UCHAR ucSS_Id; 3934 USHORT usLCDVenderID; 3935 USHORT usLCDProductID; 3936 UCHAR ucLCDPanel_SpecialHandlingCap; 3937 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3938 UCHAR ucReserved[2]; 3939}ATOM_LVDS_INFO_V12; 3940 3941//Definitions for ucLCDPanel_SpecialHandlingCap: 3942 3943//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3944//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3945#define LCDPANEL_CAP_READ_EDID 0x1 3946 3947//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3948//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3949//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3950#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3951 3952//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3953#define LCDPANEL_CAP_eDP 0x4 3954 3955 3956//Color Bit Depth definition in EDID V1.4 @BYTE 14h 3957//Bit 6 5 4 3958 // 0 0 0 - Color bit depth is undefined 3959 // 0 0 1 - 6 Bits per Primary Color 3960 // 0 1 0 - 8 Bits per Primary Color 3961 // 0 1 1 - 10 Bits per Primary Color 3962 // 1 0 0 - 12 Bits per Primary Color 3963 // 1 0 1 - 14 Bits per Primary Color 3964 // 1 1 0 - 16 Bits per Primary Color 3965 // 1 1 1 - Reserved 3966 3967#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3968 3969// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3970#define PANEL_RANDOM_DITHER 0x80 3971#define PANEL_RANDOM_DITHER_MASK 0x80 3972 3973#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3974 3975 3976typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3977{ 3978 UCHAR ucSupportedRefreshRate; 3979 UCHAR ucMinRefreshRateForDRR; 3980}ATOM_LCD_REFRESH_RATE_SUPPORT; 3981 3982/****************************************************************************/ 3983// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3984// ASIC Families: NI 3985// ucTableFormatRevision=1 3986// ucTableContentRevision=3 3987/****************************************************************************/ 3988typedef struct _ATOM_LCD_INFO_V13 3989{ 3990 ATOM_COMMON_TABLE_HEADER sHeader; 3991 ATOM_DTD_FORMAT sLCDTiming; 3992 USHORT usExtInfoTableOffset; 3993 union 3994 { 3995 USHORT usSupportedRefreshRate; 3996 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 3997 }; 3998 ULONG ulReserved0; 3999 UCHAR ucLCD_Misc; // Reorganized in V13 4000 // Bit0: {=0:single, =1:dual}, 4001 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 4002 // Bit3:2: {Grey level} 4003 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 4004 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 4005 UCHAR ucPanelDefaultRefreshRate; 4006 UCHAR ucPanelIdentification; 4007 UCHAR ucSS_Id; 4008 USHORT usLCDVenderID; 4009 USHORT usLCDProductID; 4010 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 4011 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 4012 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 4013 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 4014 // Bit7-3: Reserved 4015 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 4016 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 4017 4018 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 4019 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 4020 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 4021 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 4022 4023 UCHAR ucOffDelay_in4Ms; 4024 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 4025 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 4026 UCHAR ucReserved1; 4027 4028 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 4029 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 4030 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 4031 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 4032 4033 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 4034 UCHAR uceDPToLVDSRxId; 4035 UCHAR ucLcdReservd; 4036 ULONG ulReserved[2]; 4037}ATOM_LCD_INFO_V13; 4038 4039#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 4040 4041//Definitions for ucLCD_Misc 4042#define ATOM_PANEL_MISC_V13_DUAL 0x00000001 4043#define ATOM_PANEL_MISC_V13_FPDI 0x00000002 4044#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 4045#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 4046#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 4047#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 4048#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 4049 4050//Color Bit Depth definition in EDID V1.4 @BYTE 14h 4051//Bit 6 5 4 4052 // 0 0 0 - Color bit depth is undefined 4053 // 0 0 1 - 6 Bits per Primary Color 4054 // 0 1 0 - 8 Bits per Primary Color 4055 // 0 1 1 - 10 Bits per Primary Color 4056 // 1 0 0 - 12 Bits per Primary Color 4057 // 1 0 1 - 14 Bits per Primary Color 4058 // 1 1 0 - 16 Bits per Primary Color 4059 // 1 1 1 - Reserved 4060 4061//Definitions for ucLCDPanel_SpecialHandlingCap: 4062 4063//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 4064//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 4065#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 4066 4067//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 4068//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 4069//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 4070#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 4071 4072//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 4073#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 4074 4075//uceDPToLVDSRxId 4076#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 4077#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 4078#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 4079 4080typedef struct _ATOM_PATCH_RECORD_MODE 4081{ 4082 UCHAR ucRecordType; 4083 USHORT usHDisp; 4084 USHORT usVDisp; 4085}ATOM_PATCH_RECORD_MODE; 4086 4087typedef struct _ATOM_LCD_RTS_RECORD 4088{ 4089 UCHAR ucRecordType; 4090 UCHAR ucRTSValue; 4091}ATOM_LCD_RTS_RECORD; 4092 4093//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 4094// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 4095typedef struct _ATOM_LCD_MODE_CONTROL_CAP 4096{ 4097 UCHAR ucRecordType; 4098 USHORT usLCDCap; 4099}ATOM_LCD_MODE_CONTROL_CAP; 4100 4101#define LCD_MODE_CAP_BL_OFF 1 4102#define LCD_MODE_CAP_CRTC_OFF 2 4103#define LCD_MODE_CAP_PANEL_OFF 4 4104 4105 4106typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 4107{ 4108 UCHAR ucRecordType; 4109 UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 4110 UCHAR ucFakeEDIDString[]; // This actually has ucFakeEdidLength elements. 4111} ATOM_FAKE_EDID_PATCH_RECORD; 4112 4113typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 4114{ 4115 UCHAR ucRecordType; 4116 USHORT usHSize; 4117 USHORT usVSize; 4118}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 4119 4120#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 4121#define LCD_RTS_RECORD_TYPE 2 4122#define LCD_CAP_RECORD_TYPE 3 4123#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 4124#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 4125#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 4126#define ATOM_RECORD_END_TYPE 0xFF 4127 4128/****************************Spread Spectrum Info Table Definitions **********************/ 4129 4130//ucTableFormatRevision=1 4131//ucTableContentRevision=2 4132typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 4133{ 4134 USHORT usSpreadSpectrumPercentage; 4135 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 4136 UCHAR ucSS_Step; 4137 UCHAR ucSS_Delay; 4138 UCHAR ucSS_Id; 4139 UCHAR ucRecommendedRef_Div; 4140 UCHAR ucSS_Range; //it was reserved for V11 4141}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 4142 4143#define ATOM_MAX_SS_ENTRY 16 4144#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 4145#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 4146#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 4147#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 4148 4149 4150 4151#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 4152#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 4153#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 4154#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 4155#define ATOM_INTERNAL_SS_MASK 0x00000000 4156#define ATOM_EXTERNAL_SS_MASK 0x00000002 4157#define EXEC_SS_STEP_SIZE_SHIFT 2 4158#define EXEC_SS_DELAY_SHIFT 4 4159#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 4160 4161typedef struct _ATOM_SPREAD_SPECTRUM_INFO 4162{ 4163 ATOM_COMMON_TABLE_HEADER sHeader; 4164 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 4165}ATOM_SPREAD_SPECTRUM_INFO; 4166 4167 4168/****************************************************************************/ 4169// Structure used in AnalogTV_InfoTable (Top level) 4170/****************************************************************************/ 4171//ucTVBootUpDefaultStd definiton: 4172 4173//ATOM_TV_NTSC 1 4174//ATOM_TV_NTSCJ 2 4175//ATOM_TV_PAL 3 4176//ATOM_TV_PALM 4 4177//ATOM_TV_PALCN 5 4178//ATOM_TV_PALN 6 4179//ATOM_TV_PAL60 7 4180//ATOM_TV_SECAM 8 4181 4182//ucTVSuppportedStd definition: 4183#define NTSC_SUPPORT 0x1 4184#define NTSCJ_SUPPORT 0x2 4185 4186#define PAL_SUPPORT 0x4 4187#define PALM_SUPPORT 0x8 4188#define PALCN_SUPPORT 0x10 4189#define PALN_SUPPORT 0x20 4190#define PAL60_SUPPORT 0x40 4191#define SECAM_SUPPORT 0x80 4192 4193#define MAX_SUPPORTED_TV_TIMING 2 4194 4195typedef struct _ATOM_ANALOG_TV_INFO 4196{ 4197 ATOM_COMMON_TABLE_HEADER sHeader; 4198 UCHAR ucTV_SuppportedStandard; 4199 UCHAR ucTV_BootUpDefaultStandard; 4200 UCHAR ucExt_TV_ASIC_ID; 4201 UCHAR ucExt_TV_ASIC_SlaveAddr; 4202 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 4203}ATOM_ANALOG_TV_INFO; 4204 4205typedef struct _ATOM_DPCD_INFO 4206{ 4207 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 4208 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 4210 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 4211}ATOM_DPCD_INFO; 4212 4213#define ATOM_DPCD_MAX_LANE_MASK 0x1F 4214 4215/**************************************************************************/ 4216// VRAM usage and their defintions 4217 4218// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 4219// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 4220// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 4221// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 4222// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 4223 4224// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 4225//#ifndef VESA_MEMORY_IN_64K_BLOCK 4226//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 4227//#endif 4228 4229#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 4230#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 4231#define ATOM_HWICON_INFOTABLE_SIZE 32 4232#define MAX_DTD_MODE_IN_VRAM 6 4233#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 4234#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 4235//20 bytes for Encoder Type and DPCD in STD EDID area 4236#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 4237#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 4238 4239#define ATOM_HWICON1_SURFACE_ADDR 0 4240#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4241#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4242#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 4243#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4244#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4245 4246#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4247#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4248#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4249 4250#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4251 4252#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4253#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4254#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4255 4256#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4257#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4258#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4259 4260#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4261#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4262#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4263 4264#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4265#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4266#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4267 4268#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4269#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4270#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4271 4272#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4273#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4274#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4275 4276#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4277#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4278#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4279 4280#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4281#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4282#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4283 4284#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4285#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4286#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4287 4288#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4289 4290#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 4291#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 4292 4293//The size below is in Kb! 4294#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 4295 4296#define ATOM_VRAM_RESERVE_V2_SIZE 32 4297 4298#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 4299#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 4300#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 4301#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 4302#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2 4303 4304/***********************************************************************************/ 4305// Structure used in VRAM_UsageByFirmwareTable 4306// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 4307// at running time. 4308// note2: From RV770, the memory is more than 32bit addressable, so we will change 4309// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 4310// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 4311// (in offset to start of memory address) is KB aligned instead of byte aligend. 4312// Note3: 4313/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 4314constant across VGA or non VGA adapter, 4315for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 4316 4317If (ulStartAddrUsedByFirmware!=0) 4318FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 4319Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 4320else //Non VGA case 4321 if (FB_Size<=2Gb) 4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 4323 else 4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 4325 4326CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 4327 4328/***********************************************************************************/ 4329#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 4330 4331typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 4332{ 4333 ULONG ulStartAddrUsedByFirmware; 4334 USHORT usFirmwareUseInKb; 4335 USHORT usReserved; 4336}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 4337 4338typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 4339{ 4340 ATOM_COMMON_TABLE_HEADER sHeader; 4341 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4342}ATOM_VRAM_USAGE_BY_FIRMWARE; 4343 4344// change verion to 1.5, when allow driver to allocate the vram area for command table access. 4345typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 4346{ 4347 ULONG ulStartAddrUsedByFirmware; 4348 USHORT usFirmwareUseInKb; 4349 USHORT usFBUsedByDrvInKb; 4350}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 4351 4352typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 4353{ 4354 ATOM_COMMON_TABLE_HEADER sHeader; 4355 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4356}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 4357 4358/****************************************************************************/ 4359// Structure used in GPIO_Pin_LUTTable 4360/****************************************************************************/ 4361typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 4362{ 4363 USHORT usGpioPin_AIndex; 4364 UCHAR ucGpioPinBitShift; 4365 UCHAR ucGPIO_ID; 4366}ATOM_GPIO_PIN_ASSIGNMENT; 4367 4368//ucGPIO_ID pre-define id for multiple usage 4369// GPIO use to control PCIE_VDDC in certain SLT board 4370#define PCIE_VDDC_CONTROL_GPIO_PINID 56 4371 4372//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 4373#define PP_AC_DC_SWITCH_GPIO_PINID 60 4374//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4375#define VDDC_VRHOT_GPIO_PINID 61 4376//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4377#define VDDC_PCC_GPIO_PINID 62 4378// Only used on certain SLT/PA board to allow utility to cut Efuse. 4379#define EFUSE_CUT_ENABLE_GPIO_PINID 63 4380// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4381#define DRAM_SELF_REFRESH_GPIO_PINID 64 4382// Thermal interrupt output->system thermal chip GPIO pin 4383#define THERMAL_INT_OUTPUT_GPIO_PINID 65 4384 4385 4386typedef struct _ATOM_GPIO_PIN_LUT 4387{ 4388 ATOM_COMMON_TABLE_HEADER sHeader; 4389 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[]; 4390}ATOM_GPIO_PIN_LUT; 4391 4392/****************************************************************************/ 4393// Structure used in ComponentVideoInfoTable 4394/****************************************************************************/ 4395#define GPIO_PIN_ACTIVE_HIGH 0x1 4396#define MAX_SUPPORTED_CV_STANDARDS 5 4397 4398// definitions for ATOM_D_INFO.ucSettings 4399#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4400#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4401#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4402 4403typedef struct _ATOM_GPIO_INFO 4404{ 4405 USHORT usAOffset; 4406 UCHAR ucSettings; 4407 UCHAR ucReserved; 4408}ATOM_GPIO_INFO; 4409 4410// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4411#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4412 4413// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4414#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4415#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4416 4417// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4418//Line 3 out put 5V. 4419#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4420#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4421#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4422 4423//Line 3 out put 2.2V 4424#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4425#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4426#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4427 4428//Line 3 out put 0V 4429#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4430#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4431#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4432 4433#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4434 4435#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4436 4437//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4438#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4439#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4440 4441 4442typedef struct _ATOM_COMPONENT_VIDEO_INFO 4443{ 4444 ATOM_COMMON_TABLE_HEADER sHeader; 4445 USHORT usMask_PinRegisterIndex; 4446 USHORT usEN_PinRegisterIndex; 4447 USHORT usY_PinRegisterIndex; 4448 USHORT usA_PinRegisterIndex; 4449 UCHAR ucBitShift; 4450 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4451 ATOM_DTD_FORMAT sReserved; // must be zeroed out 4452 UCHAR ucMiscInfo; 4453 UCHAR uc480i; 4454 UCHAR uc480p; 4455 UCHAR uc720p; 4456 UCHAR uc1080i; 4457 UCHAR ucLetterBoxMode; 4458 UCHAR ucReserved[3]; 4459 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4460 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4461 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4462}ATOM_COMPONENT_VIDEO_INFO; 4463 4464//ucTableFormatRevision=2 4465//ucTableContentRevision=1 4466typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4467{ 4468 ATOM_COMMON_TABLE_HEADER sHeader; 4469 UCHAR ucMiscInfo; 4470 UCHAR uc480i; 4471 UCHAR uc480p; 4472 UCHAR uc720p; 4473 UCHAR uc1080i; 4474 UCHAR ucReserved; 4475 UCHAR ucLetterBoxMode; 4476 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4477 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4478 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4479}ATOM_COMPONENT_VIDEO_INFO_V21; 4480 4481#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4482 4483/****************************************************************************/ 4484// Structure used in object_InfoTable 4485/****************************************************************************/ 4486typedef struct _ATOM_OBJECT_HEADER 4487{ 4488 ATOM_COMMON_TABLE_HEADER sHeader; 4489 USHORT usDeviceSupport; 4490 USHORT usConnectorObjectTableOffset; 4491 USHORT usRouterObjectTableOffset; 4492 USHORT usEncoderObjectTableOffset; 4493 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4494 USHORT usDisplayPathTableOffset; 4495}ATOM_OBJECT_HEADER; 4496 4497typedef struct _ATOM_OBJECT_HEADER_V3 4498{ 4499 ATOM_COMMON_TABLE_HEADER sHeader; 4500 USHORT usDeviceSupport; 4501 USHORT usConnectorObjectTableOffset; 4502 USHORT usRouterObjectTableOffset; 4503 USHORT usEncoderObjectTableOffset; 4504 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4505 USHORT usDisplayPathTableOffset; 4506 USHORT usMiscObjectTableOffset; 4507}ATOM_OBJECT_HEADER_V3; 4508 4509 4510typedef struct _ATOM_DISPLAY_OBJECT_PATH 4511{ 4512 USHORT usDeviceTag; //supported device 4513 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4514 USHORT usConnObjectId; //Connector Object ID 4515 USHORT usGPUObjectId; //GPU ID 4516 USHORT usGraphicObjIds[]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4517}ATOM_DISPLAY_OBJECT_PATH; 4518 4519typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4520{ 4521 USHORT usDeviceTag; //supported device 4522 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4523 USHORT usConnObjectId; //Connector Object ID 4524 USHORT usGPUObjectId; //GPU ID 4525 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4526}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4527 4528typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4529{ 4530 UCHAR ucNumOfDispPath; 4531 UCHAR ucVersion; 4532 UCHAR ucPadding[2]; 4533 ATOM_DISPLAY_OBJECT_PATH asDispPath[]; 4534}ATOM_DISPLAY_OBJECT_PATH_TABLE; 4535 4536typedef struct _ATOM_OBJECT //each object has this structure 4537{ 4538 USHORT usObjectID; 4539 USHORT usSrcDstTableOffset; 4540 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4541 USHORT usReserved; 4542}ATOM_OBJECT; 4543 4544typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4545{ 4546 UCHAR ucNumberOfObjects; 4547 UCHAR ucPadding[3]; 4548 ATOM_OBJECT asObjects[]; 4549}ATOM_OBJECT_TABLE; 4550 4551typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4552{ 4553 UCHAR ucNumberOfSrc; 4554 USHORT usSrcObjectID[1]; 4555 UCHAR ucNumberOfDst; 4556 USHORT usDstObjectID[1]; 4557}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4558 4559 4560//Two definitions below are for OPM on MXM module designs 4561 4562#define EXT_HPDPIN_LUTINDEX_0 0 4563#define EXT_HPDPIN_LUTINDEX_1 1 4564#define EXT_HPDPIN_LUTINDEX_2 2 4565#define EXT_HPDPIN_LUTINDEX_3 3 4566#define EXT_HPDPIN_LUTINDEX_4 4 4567#define EXT_HPDPIN_LUTINDEX_5 5 4568#define EXT_HPDPIN_LUTINDEX_6 6 4569#define EXT_HPDPIN_LUTINDEX_7 7 4570#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4571 4572#define EXT_AUXDDC_LUTINDEX_0 0 4573#define EXT_AUXDDC_LUTINDEX_1 1 4574#define EXT_AUXDDC_LUTINDEX_2 2 4575#define EXT_AUXDDC_LUTINDEX_3 3 4576#define EXT_AUXDDC_LUTINDEX_4 4 4577#define EXT_AUXDDC_LUTINDEX_5 5 4578#define EXT_AUXDDC_LUTINDEX_6 6 4579#define EXT_AUXDDC_LUTINDEX_7 7 4580#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4581 4582//ucChannelMapping are defined as following 4583//for DP connector, eDP, DP to VGA/LVDS 4584//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4585//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4586//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4587//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4588typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4589{ 4590#if ATOM_BIG_ENDIAN 4591 UCHAR ucDP_Lane3_Source:2; 4592 UCHAR ucDP_Lane2_Source:2; 4593 UCHAR ucDP_Lane1_Source:2; 4594 UCHAR ucDP_Lane0_Source:2; 4595#else 4596 UCHAR ucDP_Lane0_Source:2; 4597 UCHAR ucDP_Lane1_Source:2; 4598 UCHAR ucDP_Lane2_Source:2; 4599 UCHAR ucDP_Lane3_Source:2; 4600#endif 4601}ATOM_DP_CONN_CHANNEL_MAPPING; 4602 4603//for DVI/HDMI, in dual link case, both links have to have same mapping. 4604//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4605//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4606//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4607//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4608typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4609{ 4610#if ATOM_BIG_ENDIAN 4611 UCHAR ucDVI_CLK_Source:2; 4612 UCHAR ucDVI_DATA0_Source:2; 4613 UCHAR ucDVI_DATA1_Source:2; 4614 UCHAR ucDVI_DATA2_Source:2; 4615#else 4616 UCHAR ucDVI_DATA2_Source:2; 4617 UCHAR ucDVI_DATA1_Source:2; 4618 UCHAR ucDVI_DATA0_Source:2; 4619 UCHAR ucDVI_CLK_Source:2; 4620#endif 4621}ATOM_DVI_CONN_CHANNEL_MAPPING; 4622 4623typedef struct _EXT_DISPLAY_PATH 4624{ 4625 USHORT usDeviceTag; //A bit vector to show what devices are supported 4626 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4627 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4628 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4629 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4630 USHORT usExtEncoderObjId; //external encoder object id 4631 union{ 4632 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4633 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4634 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4635 }; 4636 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4637 USHORT usCaps; 4638 USHORT usReserved; 4639}EXT_DISPLAY_PATH; 4640 4641#define NUMBER_OF_UCHAR_FOR_GUID 16 4642#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4643 4644//usCaps 4645#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001 4646#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002 4647#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C 4648#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip 4649#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip 4650#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip 4651 4652 4653 4654 4655typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4656{ 4657 ATOM_COMMON_TABLE_HEADER sHeader; 4658 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4659 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4660 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4661 UCHAR uc3DStereoPinId; // use for eDP panel 4662 UCHAR ucRemoteDisplayConfig; 4663 UCHAR uceDPToLVDSRxId; 4664 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4665 UCHAR Reserved[3]; // for potential expansion 4666}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4667 4668//Related definitions, all records are different but they have a common header 4669typedef struct _ATOM_COMMON_RECORD_HEADER 4670{ 4671 UCHAR ucRecordType; //An emun to indicate the record type 4672 UCHAR ucRecordSize; //The size of the whole record in byte 4673}ATOM_COMMON_RECORD_HEADER; 4674 4675 4676#define ATOM_I2C_RECORD_TYPE 1 4677#define ATOM_HPD_INT_RECORD_TYPE 2 4678#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4679#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4680#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4681#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4682#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4683#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4684#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4685#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4686#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4687#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4688#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4689#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4690#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4691#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4692#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4693#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4694#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4695#define ATOM_ENCODER_CAP_RECORD_TYPE 20 4696#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4697#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22 4698 4699//Must be updated when new record type is added,equal to that record definition! 4700#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 4701 4702typedef struct _ATOM_I2C_RECORD 4703{ 4704 ATOM_COMMON_RECORD_HEADER sheader; 4705 ATOM_I2C_ID_CONFIG sucI2cId; 4706 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4707}ATOM_I2C_RECORD; 4708 4709typedef struct _ATOM_HPD_INT_RECORD 4710{ 4711 ATOM_COMMON_RECORD_HEADER sheader; 4712 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4713 UCHAR ucPlugged_PinState; 4714}ATOM_HPD_INT_RECORD; 4715 4716 4717typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4718{ 4719 ATOM_COMMON_RECORD_HEADER sheader; 4720 UCHAR ucProtectionFlag; 4721 UCHAR ucReserved; 4722}ATOM_OUTPUT_PROTECTION_RECORD; 4723 4724typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4725{ 4726 ULONG ulACPIDeviceEnum; //Reserved for now 4727 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4728 USHORT usPadding; 4729}ATOM_CONNECTOR_DEVICE_TAG; 4730 4731typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4732{ 4733 ATOM_COMMON_RECORD_HEADER sheader; 4734 UCHAR ucNumberOfDevice; 4735 UCHAR ucReserved; 4736 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4737}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4738 4739 4740typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4741{ 4742 ATOM_COMMON_RECORD_HEADER sheader; 4743 UCHAR ucConfigGPIOID; 4744 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4745 UCHAR ucFlowinGPIPID; 4746 UCHAR ucExtInGPIPID; 4747}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4748 4749typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4750{ 4751 ATOM_COMMON_RECORD_HEADER sheader; 4752 UCHAR ucCTL1GPIO_ID; 4753 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4754 UCHAR ucCTL2GPIO_ID; 4755 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4756 UCHAR ucCTL3GPIO_ID; 4757 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4758 UCHAR ucCTLFPGA_IN_ID; 4759 UCHAR ucPadding[3]; 4760}ATOM_ENCODER_FPGA_CONTROL_RECORD; 4761 4762typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4763{ 4764 ATOM_COMMON_RECORD_HEADER sheader; 4765 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4766 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4767}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4768 4769typedef struct _ATOM_JTAG_RECORD 4770{ 4771 ATOM_COMMON_RECORD_HEADER sheader; 4772 UCHAR ucTMSGPIO_ID; 4773 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4774 UCHAR ucTCKGPIO_ID; 4775 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4776 UCHAR ucTDOGPIO_ID; 4777 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4778 UCHAR ucTDIGPIO_ID; 4779 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4780 UCHAR ucPadding[2]; 4781}ATOM_JTAG_RECORD; 4782 4783 4784//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4785typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4786{ 4787 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4789}ATOM_GPIO_PIN_CONTROL_PAIR; 4790 4791typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4792{ 4793 ATOM_COMMON_RECORD_HEADER sheader; 4794 UCHAR ucFlags; // Future expnadibility 4795 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4796 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4797}ATOM_OBJECT_GPIO_CNTL_RECORD; 4798 4799//Definitions for GPIO pin state 4800#define GPIO_PIN_TYPE_INPUT 0x00 4801#define GPIO_PIN_TYPE_OUTPUT 0x10 4802#define GPIO_PIN_TYPE_HW_CONTROL 0x20 4803 4804//For GPIO_PIN_TYPE_OUTPUT the following is defined 4805#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4806#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4807#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4808#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4809 4810// Indexes to GPIO array in GLSync record 4811// GLSync record is for Frame Lock/Gen Lock feature. 4812#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4813#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4814#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4815#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4816#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4817#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4818#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4819#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4820#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4821#define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4822 4823typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4824{ 4825 ATOM_COMMON_RECORD_HEADER sheader; 4826 ULONG ulStrengthControl; // DVOA strength control for CF 4827 UCHAR ucPadding[2]; 4828}ATOM_ENCODER_DVO_CF_RECORD; 4829 4830// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 4831#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 4832#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. 4833#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4834#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4835#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board. 4836 4837typedef struct _ATOM_ENCODER_CAP_RECORD 4838{ 4839 ATOM_COMMON_RECORD_HEADER sheader; 4840 union { 4841 USHORT usEncoderCap; 4842 struct { 4843#if ATOM_BIG_ENDIAN 4844 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4845 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4846 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4847#else 4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4849 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4850 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4851#endif 4852 }; 4853 }; 4854}ATOM_ENCODER_CAP_RECORD; 4855 4856// Used after SI 4857typedef struct _ATOM_ENCODER_CAP_RECORD_V2 4858{ 4859 ATOM_COMMON_RECORD_HEADER sheader; 4860 union { 4861 USHORT usEncoderCap; 4862 struct { 4863#if ATOM_BIG_ENDIAN 4864 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4865 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4866 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4867 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4868 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4869#else 4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4871 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4872 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4873 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4874 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4875#endif 4876 }; 4877 }; 4878}ATOM_ENCODER_CAP_RECORD_V2; 4879 4880 4881// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4882#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4883#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4884 4885typedef struct _ATOM_CONNECTOR_CF_RECORD 4886{ 4887 ATOM_COMMON_RECORD_HEADER sheader; 4888 USHORT usMaxPixClk; 4889 UCHAR ucFlowCntlGpioId; 4890 UCHAR ucSwapCntlGpioId; 4891 UCHAR ucConnectedDvoBundle; 4892 UCHAR ucPadding; 4893}ATOM_CONNECTOR_CF_RECORD; 4894 4895typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4896{ 4897 ATOM_COMMON_RECORD_HEADER sheader; 4898 ATOM_DTD_FORMAT asTiming; 4899}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4900 4901typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4902{ 4903 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4904 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4905 UCHAR ucReserved; 4906}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4907 4908 4909typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4910{ 4911 ATOM_COMMON_RECORD_HEADER sheader; 4912 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4913 UCHAR ucMuxControlPin; 4914 UCHAR ucMuxState[2]; //for alligment purpose 4915}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4916 4917typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4918{ 4919 ATOM_COMMON_RECORD_HEADER sheader; 4920 UCHAR ucMuxType; 4921 UCHAR ucMuxControlPin; 4922 UCHAR ucMuxState[2]; //for alligment purpose 4923}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4924 4925// define ucMuxType 4926#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4927#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4928 4929typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4930{ 4931 ATOM_COMMON_RECORD_HEADER sheader; 4932 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4933}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4934 4935typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4936{ 4937 ATOM_COMMON_RECORD_HEADER sheader; 4938 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4939}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4940 4941typedef struct _ATOM_OBJECT_LINK_RECORD 4942{ 4943 ATOM_COMMON_RECORD_HEADER sheader; 4944 USHORT usObjectID; //could be connector, encorder or other object in object.h 4945}ATOM_OBJECT_LINK_RECORD; 4946 4947typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4948{ 4949 ATOM_COMMON_RECORD_HEADER sheader; 4950 USHORT usReserved; 4951}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4952 4953 4954typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD 4955{ 4956 ATOM_COMMON_RECORD_HEADER sheader; 4957 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 4958 UCHAR ucMaxTmdsClkRateIn2_5Mhz; 4959 UCHAR ucReserved; 4960} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; 4961 4962 4963typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4964{ 4965 USHORT usConnectorObjectId; 4966 UCHAR ucConnectorType; 4967 UCHAR ucPosition; 4968}ATOM_CONNECTOR_LAYOUT_INFO; 4969 4970// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4971#define CONNECTOR_TYPE_DVI_D 1 4972#define CONNECTOR_TYPE_DVI_I 2 4973#define CONNECTOR_TYPE_VGA 3 4974#define CONNECTOR_TYPE_HDMI 4 4975#define CONNECTOR_TYPE_DISPLAY_PORT 5 4976#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4977 4978typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4979{ 4980 ATOM_COMMON_RECORD_HEADER sheader; 4981 UCHAR ucLength; 4982 UCHAR ucWidth; 4983 UCHAR ucConnNum; 4984 UCHAR ucReserved; 4985 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[]; 4986}ATOM_BRACKET_LAYOUT_RECORD; 4987 4988 4989/****************************************************************************/ 4990// Structure used in XXXX 4991/****************************************************************************/ 4992typedef struct _ATOM_VOLTAGE_INFO_HEADER 4993{ 4994 USHORT usVDDCBaseLevel; //In number of 50mv unit 4995 USHORT usReserved; //For possible extension table offset 4996 UCHAR ucNumOfVoltageEntries; 4997 UCHAR ucBytesPerVoltageEntry; 4998 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4999 UCHAR ucDefaultVoltageEntry; 5000 UCHAR ucVoltageControlI2cLine; 5001 UCHAR ucVoltageControlAddress; 5002 UCHAR ucVoltageControlOffset; 5003}ATOM_VOLTAGE_INFO_HEADER; 5004 5005typedef struct _ATOM_VOLTAGE_INFO 5006{ 5007 ATOM_COMMON_TABLE_HEADER sHeader; 5008 ATOM_VOLTAGE_INFO_HEADER viHeader; 5009 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 5010}ATOM_VOLTAGE_INFO; 5011 5012 5013typedef struct _ATOM_VOLTAGE_FORMULA 5014{ 5015 USHORT usVoltageBaseLevel; // In number of 1mv unit 5016 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 5017 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5018 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 5019 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 5020 UCHAR ucReserved; 5021 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 5022}ATOM_VOLTAGE_FORMULA; 5023 5024typedef struct _VOLTAGE_LUT_ENTRY 5025{ 5026 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 5027 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5028}VOLTAGE_LUT_ENTRY; 5029 5030typedef struct _ATOM_VOLTAGE_FORMULA_V2 5031{ 5032 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5033 UCHAR ucReserved[3]; 5034 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 5035}ATOM_VOLTAGE_FORMULA_V2; 5036 5037typedef struct _ATOM_VOLTAGE_CONTROL 5038{ 5039 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 5040 UCHAR ucVoltageControlI2cLine; 5041 UCHAR ucVoltageControlAddress; 5042 UCHAR ucVoltageControlOffset; 5043 USHORT usGpioPin_AIndex; //GPIO_PAD register index 5044 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 5045 UCHAR ucReserved; 5046}ATOM_VOLTAGE_CONTROL; 5047 5048// Define ucVoltageControlId 5049#define VOLTAGE_CONTROLLED_BY_HW 0x00 5050#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 5051#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 5052#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 5053#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 5054#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 5055#define VOLTAGE_CONTROL_ID_DS4402 0x04 5056#define VOLTAGE_CONTROL_ID_UP6266 0x05 5057#define VOLTAGE_CONTROL_ID_SCORPIO 0x06 5058#define VOLTAGE_CONTROL_ID_VT1556M 0x07 5059#define VOLTAGE_CONTROL_ID_CHL822x 0x08 5060#define VOLTAGE_CONTROL_ID_VT1586M 0x09 5061#define VOLTAGE_CONTROL_ID_UP1637 0x0A 5062#define VOLTAGE_CONTROL_ID_CHL8214 0x0B 5063#define VOLTAGE_CONTROL_ID_UP1801 0x0C 5064#define VOLTAGE_CONTROL_ID_ST6788A 0x0D 5065#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 5066#define VOLTAGE_CONTROL_ID_AD527x 0x0F 5067#define VOLTAGE_CONTROL_ID_NCP81022 0x10 5068#define VOLTAGE_CONTROL_ID_LTC2635 0x11 5069#define VOLTAGE_CONTROL_ID_NCP4208 0x12 5070#define VOLTAGE_CONTROL_ID_IR35xx 0x13 5071#define VOLTAGE_CONTROL_ID_RT9403 0x14 5072 5073#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 5074 5075typedef struct _ATOM_VOLTAGE_OBJECT 5076{ 5077 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5078 UCHAR ucSize; //Size of Object 5079 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5080 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 5081}ATOM_VOLTAGE_OBJECT; 5082 5083typedef struct _ATOM_VOLTAGE_OBJECT_V2 5084{ 5085 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5086 UCHAR ucSize; //Size of Object 5087 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5088 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 5089}ATOM_VOLTAGE_OBJECT_V2; 5090 5091typedef struct _ATOM_VOLTAGE_OBJECT_INFO 5092{ 5093 ATOM_COMMON_TABLE_HEADER sHeader; 5094 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 5095}ATOM_VOLTAGE_OBJECT_INFO; 5096 5097typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 5098{ 5099 ATOM_COMMON_TABLE_HEADER sHeader; 5100 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 5101}ATOM_VOLTAGE_OBJECT_INFO_V2; 5102 5103typedef struct _ATOM_LEAKID_VOLTAGE 5104{ 5105 UCHAR ucLeakageId; 5106 UCHAR ucReserved; 5107 USHORT usVoltage; 5108}ATOM_LEAKID_VOLTAGE; 5109 5110typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 5111 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5112 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 5113 USHORT usSize; //Size of Object 5114}ATOM_VOLTAGE_OBJECT_HEADER_V3; 5115 5116// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 5117#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5118#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 5119#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5120#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 5121#define VOLTAGE_OBJ_EVV 8 5122#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5123#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5124#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5125 5126typedef struct _VOLTAGE_LUT_ENTRY_V2 5127{ 5128 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 5129 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5130}VOLTAGE_LUT_ENTRY_V2; 5131 5132typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 5133{ 5134 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 5135 USHORT usVoltageId; 5136 USHORT usLeakageId; // The corresponding Voltage Value, in mV 5137}LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 5138 5139 5140typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 5141{ 5142 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 5143 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 5144 UCHAR ucVoltageControlI2cLine; 5145 UCHAR ucVoltageControlAddress; 5146 UCHAR ucVoltageControlOffset; 5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 5148 UCHAR ulReserved[3]; 5149 VOLTAGE_LUT_ENTRY asVolI2cLut[]; // end with 0xff 5150}ATOM_I2C_VOLTAGE_OBJECT_V3; 5151 5152// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 5153#define VOLTAGE_DATA_ONE_BYTE 0 5154#define VOLTAGE_DATA_TWO_BYTE 1 5155 5156typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 5157{ 5158 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 5159 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 5160 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 5161 UCHAR ucPhaseDelay; // phase delay in unit of micro second 5162 UCHAR ucReserved; 5163 ULONG ulGpioMaskVal; // GPIO Mask value 5164 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[]; 5165}ATOM_GPIO_VOLTAGE_OBJECT_V3; 5166 5167typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5168{ 5169 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 5170 UCHAR ucLeakageCntlId; // default is 0 5171 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 5172 UCHAR ucReserved[2]; 5173 ULONG ulMaxVoltageLevel; 5174 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[]; 5175}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 5176 5177 5178typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 5179{ 5180 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5181// 14:7 - PSI0_VID 5182// 6 - PSI0_EN 5183// 5 - PSI1 5184// 4:2 - load line slope trim. 5185// 1:0 - offset trim, 5186 USHORT usLoadLine_PSI; 5187// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 5188 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 5189 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 5190 ULONG ulReserved; 5191}ATOM_SVID2_VOLTAGE_OBJECT_V3; 5192 5193 5194 5195typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3 5196{ 5197 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 5198 UCHAR ucMergedVType; // VDDC/VDCCI/.... 5199 UCHAR ucReserved[3]; 5200}ATOM_MERGED_VOLTAGE_OBJECT_V3; 5201 5202 5203typedef struct _ATOM_EVV_DPM_INFO 5204{ 5205 ULONG ulDPMSclk; // DPM state SCLK 5206 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv 5207 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable 5208 UCHAR ucDPMState; // DPMState0~7 5209} ATOM_EVV_DPM_INFO; 5210 5211// ucVoltageMode = VOLTAGE_OBJ_EVV 5212typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3 5213{ 5214 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5215 ATOM_EVV_DPM_INFO asEvvDpmList[8]; 5216}ATOM_EVV_VOLTAGE_OBJECT_V3; 5217 5218 5219typedef union _ATOM_VOLTAGE_OBJECT_V3{ 5220 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 5221 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 5222 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 5223 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 5224 ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj; 5225}ATOM_VOLTAGE_OBJECT_V3; 5226 5227typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 5228{ 5229 ATOM_COMMON_TABLE_HEADER sHeader; 5230 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 5231}ATOM_VOLTAGE_OBJECT_INFO_V3_1; 5232 5233 5234typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 5235{ 5236 UCHAR ucProfileId; 5237 UCHAR ucReserved; 5238 USHORT usSize; 5239 USHORT usEfuseSpareStartAddr; 5240 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 5241 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 5242}ATOM_ASIC_PROFILE_VOLTAGE; 5243 5244//ucProfileId 5245#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 5246#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 5247#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 5248 5249typedef struct _ATOM_ASIC_PROFILING_INFO 5250{ 5251 ATOM_COMMON_TABLE_HEADER asHeader; 5252 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 5253}ATOM_ASIC_PROFILING_INFO; 5254 5255typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 5256{ 5257 ATOM_COMMON_TABLE_HEADER asHeader; 5258 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 5259 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 5260 5261 UCHAR ucElbVDDC_Num; 5262 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 5263 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5264 5265 UCHAR ucElbVDDCI_Num; 5266 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 5267 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5268}ATOM_ASIC_PROFILING_INFO_V2_1; 5269 5270 5271//Here is parameter to convert Efuse value to Measure value 5272//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 5273typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 5274{ 5275 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5276 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5277 UCHAR ucEfuseLength; // Efuse bits length, 5278 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5279 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 5280}EFUSE_LOGISTIC_FUNC_PARAM; 5281 5282//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 5283typedef struct _EFUSE_LINEAR_FUNC_PARAM 5284{ 5285 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5286 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5287 UCHAR ucEfuseLength; // Efuse bits length, 5288 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5289 ULONG ulEfuseMin; // Min 5290}EFUSE_LINEAR_FUNC_PARAM; 5291 5292 5293typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 5294{ 5295 ATOM_COMMON_TABLE_HEADER asHeader; 5296 ULONG ulEvvDerateTdp; 5297 ULONG ulEvvDerateTdc; 5298 ULONG ulBoardCoreTemp; 5299 ULONG ulMaxVddc; 5300 ULONG ulMinVddc; 5301 ULONG ulLoadLineSlop; 5302 ULONG ulLeakageTemp; 5303 ULONG ulLeakageVoltage; 5304 EFUSE_LINEAR_FUNC_PARAM sCACm; 5305 EFUSE_LINEAR_FUNC_PARAM sCACb; 5306 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5307 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5308 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5309 USHORT usLkgEuseIndex; 5310 UCHAR ucLkgEfuseBitLSB; 5311 UCHAR ucLkgEfuseLength; 5312 ULONG ulLkgEncodeLn_MaxDivMin; 5313 ULONG ulLkgEncodeMax; 5314 ULONG ulLkgEncodeMin; 5315 ULONG ulEfuseLogisticAlpha; 5316 USHORT usPowerDpm0; 5317 USHORT usCurrentDpm0; 5318 USHORT usPowerDpm1; 5319 USHORT usCurrentDpm1; 5320 USHORT usPowerDpm2; 5321 USHORT usCurrentDpm2; 5322 USHORT usPowerDpm3; 5323 USHORT usCurrentDpm3; 5324 USHORT usPowerDpm4; 5325 USHORT usCurrentDpm4; 5326 USHORT usPowerDpm5; 5327 USHORT usCurrentDpm5; 5328 USHORT usPowerDpm6; 5329 USHORT usCurrentDpm6; 5330 USHORT usPowerDpm7; 5331 USHORT usCurrentDpm7; 5332}ATOM_ASIC_PROFILING_INFO_V3_1; 5333 5334 5335typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 5336{ 5337 ATOM_COMMON_TABLE_HEADER asHeader; 5338 ULONG ulEvvLkgFactor; 5339 ULONG ulBoardCoreTemp; 5340 ULONG ulMaxVddc; 5341 ULONG ulMinVddc; 5342 ULONG ulLoadLineSlop; 5343 ULONG ulLeakageTemp; 5344 ULONG ulLeakageVoltage; 5345 EFUSE_LINEAR_FUNC_PARAM sCACm; 5346 EFUSE_LINEAR_FUNC_PARAM sCACb; 5347 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5348 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5349 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5350 USHORT usLkgEuseIndex; 5351 UCHAR ucLkgEfuseBitLSB; 5352 UCHAR ucLkgEfuseLength; 5353 ULONG ulLkgEncodeLn_MaxDivMin; 5354 ULONG ulLkgEncodeMax; 5355 ULONG ulLkgEncodeMin; 5356 ULONG ulEfuseLogisticAlpha; 5357 USHORT usPowerDpm0; 5358 USHORT usPowerDpm1; 5359 USHORT usPowerDpm2; 5360 USHORT usPowerDpm3; 5361 USHORT usPowerDpm4; 5362 USHORT usPowerDpm5; 5363 USHORT usPowerDpm6; 5364 USHORT usPowerDpm7; 5365 ULONG ulTdpDerateDPM0; 5366 ULONG ulTdpDerateDPM1; 5367 ULONG ulTdpDerateDPM2; 5368 ULONG ulTdpDerateDPM3; 5369 ULONG ulTdpDerateDPM4; 5370 ULONG ulTdpDerateDPM5; 5371 ULONG ulTdpDerateDPM6; 5372 ULONG ulTdpDerateDPM7; 5373}ATOM_ASIC_PROFILING_INFO_V3_2; 5374 5375 5376// for Tonga/Fiji speed EVV algorithm 5377typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 5378{ 5379 ATOM_COMMON_TABLE_HEADER asHeader; 5380 ULONG ulEvvLkgFactor; 5381 ULONG ulBoardCoreTemp; 5382 ULONG ulMaxVddc; 5383 ULONG ulMinVddc; 5384 ULONG ulLoadLineSlop; 5385 ULONG ulLeakageTemp; 5386 ULONG ulLeakageVoltage; 5387 EFUSE_LINEAR_FUNC_PARAM sCACm; 5388 EFUSE_LINEAR_FUNC_PARAM sCACb; 5389 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5390 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5391 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5392 USHORT usLkgEuseIndex; 5393 UCHAR ucLkgEfuseBitLSB; 5394 UCHAR ucLkgEfuseLength; 5395 ULONG ulLkgEncodeLn_MaxDivMin; 5396 ULONG ulLkgEncodeMax; 5397 ULONG ulLkgEncodeMin; 5398 ULONG ulEfuseLogisticAlpha; 5399 5400 union{ 5401 USHORT usPowerDpm0; 5402 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive 5403 }; 5404 USHORT usPowerDpm1; 5405 USHORT usPowerDpm2; 5406 USHORT usPowerDpm3; 5407 USHORT usPowerDpm4; 5408 USHORT usPowerDpm5; 5409 USHORT usPowerDpm6; 5410 USHORT usPowerDpm7; 5411 ULONG ulTdpDerateDPM0; 5412 ULONG ulTdpDerateDPM1; 5413 ULONG ulTdpDerateDPM2; 5414 ULONG ulTdpDerateDPM3; 5415 ULONG ulTdpDerateDPM4; 5416 ULONG ulTdpDerateDPM5; 5417 ULONG ulTdpDerateDPM6; 5418 ULONG ulTdpDerateDPM7; 5419 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5420 ULONG ulRoAlpha; 5421 ULONG ulRoBeta; 5422 ULONG ulRoGamma; 5423 ULONG ulRoEpsilon; 5424 ULONG ulATermRo; 5425 ULONG ulBTermRo; 5426 ULONG ulCTermRo; 5427 ULONG ulSclkMargin; 5428 ULONG ulFmaxPercent; 5429 ULONG ulCRPercent; 5430 ULONG ulSFmaxPercent; 5431 ULONG ulSCRPercent; 5432 ULONG ulSDCMargine; 5433}ATOM_ASIC_PROFILING_INFO_V3_3; 5434 5435// for Fiji speed EVV algorithm 5436typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 5437{ 5438 ATOM_COMMON_TABLE_HEADER asHeader; 5439 ULONG ulEvvLkgFactor; 5440 ULONG ulBoardCoreTemp; 5441 ULONG ulMaxVddc; 5442 ULONG ulMinVddc; 5443 ULONG ulLoadLineSlop; 5444 ULONG ulLeakageTemp; 5445 ULONG ulLeakageVoltage; 5446 EFUSE_LINEAR_FUNC_PARAM sCACm; 5447 EFUSE_LINEAR_FUNC_PARAM sCACb; 5448 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5449 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5450 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5451 USHORT usLkgEuseIndex; 5452 UCHAR ucLkgEfuseBitLSB; 5453 UCHAR ucLkgEfuseLength; 5454 ULONG ulLkgEncodeLn_MaxDivMin; 5455 ULONG ulLkgEncodeMax; 5456 ULONG ulLkgEncodeMin; 5457 ULONG ulEfuseLogisticAlpha; 5458 USHORT usPowerDpm0; 5459 USHORT usPowerDpm1; 5460 USHORT usPowerDpm2; 5461 USHORT usPowerDpm3; 5462 USHORT usPowerDpm4; 5463 USHORT usPowerDpm5; 5464 USHORT usPowerDpm6; 5465 USHORT usPowerDpm7; 5466 ULONG ulTdpDerateDPM0; 5467 ULONG ulTdpDerateDPM1; 5468 ULONG ulTdpDerateDPM2; 5469 ULONG ulTdpDerateDPM3; 5470 ULONG ulTdpDerateDPM4; 5471 ULONG ulTdpDerateDPM5; 5472 ULONG ulTdpDerateDPM6; 5473 ULONG ulTdpDerateDPM7; 5474 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5475 ULONG ulEvvDefaultVddc; 5476 ULONG ulEvvNoCalcVddc; 5477 USHORT usParamNegFlag; 5478 USHORT usSpeed_Model; 5479 ULONG ulSM_A0; 5480 ULONG ulSM_A1; 5481 ULONG ulSM_A2; 5482 ULONG ulSM_A3; 5483 ULONG ulSM_A4; 5484 ULONG ulSM_A5; 5485 ULONG ulSM_A6; 5486 ULONG ulSM_A7; 5487 UCHAR ucSM_A0_sign; 5488 UCHAR ucSM_A1_sign; 5489 UCHAR ucSM_A2_sign; 5490 UCHAR ucSM_A3_sign; 5491 UCHAR ucSM_A4_sign; 5492 UCHAR ucSM_A5_sign; 5493 UCHAR ucSM_A6_sign; 5494 UCHAR ucSM_A7_sign; 5495 ULONG ulMargin_RO_a; 5496 ULONG ulMargin_RO_b; 5497 ULONG ulMargin_RO_c; 5498 ULONG ulMargin_fixed; 5499 ULONG ulMargin_Fmax_mean; 5500 ULONG ulMargin_plat_mean; 5501 ULONG ulMargin_Fmax_sigma; 5502 ULONG ulMargin_plat_sigma; 5503 ULONG ulMargin_DC_sigma; 5504 ULONG ulReserved[8]; // Reserved for future ASIC 5505}ATOM_ASIC_PROFILING_INFO_V3_4; 5506 5507// for Polaris10/Polaris11 speed EVV algorithm 5508typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 5509{ 5510 ATOM_COMMON_TABLE_HEADER asHeader; 5511 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv 5512 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv 5513 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address ) 5514 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD 5515 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length 5516 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 ) 5517 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5518 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5519 EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1. 5520 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/> 5521 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/> 5522 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/> 5523 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/> 5524 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/> 5525 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/> 5526 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/> 5527 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/> 5528 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/> 5529 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/> 5530 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/> 5531 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/> 5532 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/> 5533 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/> 5534 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/> 5535 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/> 5536 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/> 5537 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/> 5538 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/> 5539 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1" 5540 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1" 5541 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1" 5542 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/> 5543 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/> 5544 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/> 5545 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/> 5546 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/> 5547 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/> 5548 ULONG ulReserved[12]; 5549}ATOM_ASIC_PROFILING_INFO_V3_5; 5550 5551/* for Polars10/11 AVFS parameters */ 5552typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6 5553{ 5554 ATOM_COMMON_TABLE_HEADER asHeader; 5555 ULONG ulMaxVddc; 5556 ULONG ulMinVddc; 5557 USHORT usLkgEuseIndex; 5558 UCHAR ucLkgEfuseBitLSB; 5559 UCHAR ucLkgEfuseLength; 5560 ULONG ulLkgEncodeLn_MaxDivMin; 5561 ULONG ulLkgEncodeMax; 5562 ULONG ulLkgEncodeMin; 5563 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5564 ULONG ulEvvDefaultVddc; 5565 ULONG ulEvvNoCalcVddc; 5566 ULONG ulSpeed_Model; 5567 ULONG ulSM_A0; 5568 ULONG ulSM_A1; 5569 ULONG ulSM_A2; 5570 ULONG ulSM_A3; 5571 ULONG ulSM_A4; 5572 ULONG ulSM_A5; 5573 ULONG ulSM_A6; 5574 ULONG ulSM_A7; 5575 UCHAR ucSM_A0_sign; 5576 UCHAR ucSM_A1_sign; 5577 UCHAR ucSM_A2_sign; 5578 UCHAR ucSM_A3_sign; 5579 UCHAR ucSM_A4_sign; 5580 UCHAR ucSM_A5_sign; 5581 UCHAR ucSM_A6_sign; 5582 UCHAR ucSM_A7_sign; 5583 ULONG ulMargin_RO_a; 5584 ULONG ulMargin_RO_b; 5585 ULONG ulMargin_RO_c; 5586 ULONG ulMargin_fixed; 5587 ULONG ulMargin_Fmax_mean; 5588 ULONG ulMargin_plat_mean; 5589 ULONG ulMargin_Fmax_sigma; 5590 ULONG ulMargin_plat_sigma; 5591 ULONG ulMargin_DC_sigma; 5592 ULONG ulLoadLineSlop; 5593 ULONG ulaTDClimitPerDPM[8]; 5594 ULONG ulaNoCalcVddcPerDPM[8]; 5595 ULONG ulAVFS_meanNsigma_Acontant0; 5596 ULONG ulAVFS_meanNsigma_Acontant1; 5597 ULONG ulAVFS_meanNsigma_Acontant2; 5598 USHORT usAVFS_meanNsigma_DC_tol_sigma; 5599 USHORT usAVFS_meanNsigma_Platform_mean; 5600 USHORT usAVFS_meanNsigma_Platform_sigma; 5601 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0; 5602 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1; 5603 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2; 5604 ULONG ulGB_VDROOP_TABLE_CKSON_a0; 5605 ULONG ulGB_VDROOP_TABLE_CKSON_a1; 5606 ULONG ulGB_VDROOP_TABLE_CKSON_a2; 5607 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 5608 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2; 5609 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b; 5610 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1; 5611 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2; 5612 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b; 5613 USHORT usMaxVoltage_0_25mv; 5614 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF; 5615 UCHAR ucEnableGB_VDROOP_TABLE_CKSON; 5616 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF; 5617 UCHAR ucEnableGB_FUSE_TABLE_CKSON; 5618 USHORT usPSM_Age_ComFactor; 5619 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage; 5620 UCHAR ucReserved; 5621}ATOM_ASIC_PROFILING_INFO_V3_6; 5622 5623 5624typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ 5625 ULONG ulMaxSclkFreq; 5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz 5627 UCHAR ucPostdiv; // divide by 2^n 5628 USHORT ucFcw_pcc; 5629 USHORT ucFcw_trans_upper; 5630 USHORT ucRcw_trans_lower; 5631}ATOM_SCLK_FCW_RANGE_ENTRY_V1; 5632 5633 5634// SMU_InfoTable for Polaris10/Polaris11 5635typedef struct _ATOM_SMU_INFO_V2_1 5636{ 5637 ATOM_COMMON_TABLE_HEADER asHeader; 5638 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1 5639 UCHAR ucSMUVer; 5640 UCHAR ucSharePowerSource; 5641 UCHAR ucReserved; 5642 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8]; 5643}ATOM_SMU_INFO_V2_1; 5644 5645 5646// GFX_InfoTable for Polaris10/Polaris11 5647typedef struct _ATOM_GFX_INFO_V2_1 5648{ 5649 ATOM_COMMON_TABLE_HEADER asHeader; 5650 UCHAR GfxIpMinVer; 5651 UCHAR GfxIpMajVer; 5652 UCHAR max_shader_engines; 5653 UCHAR max_tile_pipes; 5654 UCHAR max_cu_per_sh; 5655 UCHAR max_sh_per_se; 5656 UCHAR max_backends_per_se; 5657 UCHAR max_texture_channel_caches; 5658}ATOM_GFX_INFO_V2_1; 5659 5660typedef struct _ATOM_GFX_INFO_V2_3 5661{ 5662 ATOM_COMMON_TABLE_HEADER asHeader; 5663 UCHAR GfxIpMinVer; 5664 UCHAR GfxIpMajVer; 5665 UCHAR max_shader_engines; 5666 UCHAR max_tile_pipes; 5667 UCHAR max_cu_per_sh; 5668 UCHAR max_sh_per_se; 5669 UCHAR max_backends_per_se; 5670 UCHAR max_texture_channel_caches; 5671 USHORT usHiLoLeakageThreshold; 5672 USHORT usEdcDidtLoDpm7TableOffset; //offset of DPM7 low leakage table _ATOM_EDC_DIDT_TABLE_V1 5673 USHORT usEdcDidtHiDpm7TableOffset; //offset of DPM7 high leakage table _ATOM_EDC_DIDT_TABLE_V1 5674 USHORT usReserverd[3]; 5675}ATOM_GFX_INFO_V2_3; 5676 5677typedef struct _ATOM_POWER_SOURCE_OBJECT 5678{ 5679 UCHAR ucPwrSrcId; // Power source 5680 UCHAR ucPwrSensorType; // GPIO, I2C or none 5681 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 5682 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 5683 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5684 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5685 UCHAR ucPwrSensActiveState; // high active or low active 5686 UCHAR ucReserve[3]; // reserve 5687 USHORT usSensPwr; // in unit of watt 5688}ATOM_POWER_SOURCE_OBJECT; 5689 5690typedef struct _ATOM_POWER_SOURCE_INFO 5691{ 5692 ATOM_COMMON_TABLE_HEADER asHeader; 5693 UCHAR asPwrbehave[16]; 5694 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5695}ATOM_POWER_SOURCE_INFO; 5696 5697 5698//Define ucPwrSrcId 5699#define POWERSOURCE_PCIE_ID1 0x00 5700#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5701#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5702#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5703#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5704 5705//define ucPwrSensorId 5706#define POWER_SENSOR_ALWAYS 0x00 5707#define POWER_SENSOR_GPIO 0x01 5708#define POWER_SENSOR_I2C 0x02 5709 5710typedef struct _ATOM_CLK_VOLT_CAPABILITY 5711{ 5712 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5713 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5714}ATOM_CLK_VOLT_CAPABILITY; 5715 5716 5717typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5718{ 5719 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5720 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5721}ATOM_CLK_VOLT_CAPABILITY_V2; 5722 5723typedef struct _ATOM_AVAILABLE_SCLK_LIST 5724{ 5725 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5726 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5727 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5728}ATOM_AVAILABLE_SCLK_LIST; 5729 5730// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5731#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5732 5733// this IntegrateSystemInfoTable is used for Liano/Ontario APU 5734typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5735{ 5736 ATOM_COMMON_TABLE_HEADER sHeader; 5737 ULONG ulBootUpEngineClock; 5738 ULONG ulDentistVCOFreq; 5739 ULONG ulBootUpUMAClock; 5740 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5741 ULONG ulBootUpReqDisplayVector; 5742 ULONG ulOtherDisplayMisc; 5743 ULONG ulGPUCapInfo; 5744 ULONG ulSB_MMIO_Base_Addr; 5745 USHORT usRequestedPWMFreqInHz; 5746 UCHAR ucHtcTmpLmt; 5747 UCHAR ucHtcHystLmt; 5748 ULONG ulMinEngineClock; 5749 ULONG ulSystemConfig; 5750 ULONG ulCPUCapInfo; 5751 USHORT usNBP0Voltage; 5752 USHORT usNBP1Voltage; 5753 USHORT usBootUpNBVoltage; 5754 USHORT usExtDispConnInfoOffset; 5755 USHORT usPanelRefreshRateRange; 5756 UCHAR ucMemoryType; 5757 UCHAR ucUMAChannelNumber; 5758 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5759 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5760 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5761 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5762 ULONG ulGMCRestoreResetTime; 5763 ULONG ulMinimumNClk; 5764 ULONG ulIdleNClk; 5765 ULONG ulDDR_DLL_PowerUpTime; 5766 ULONG ulDDR_PLL_PowerUpTime; 5767 USHORT usPCIEClkSSPercentage; 5768 USHORT usPCIEClkSSType; 5769 USHORT usLvdsSSPercentage; 5770 USHORT usLvdsSSpreadRateIn10Hz; 5771 USHORT usHDMISSPercentage; 5772 USHORT usHDMISSpreadRateIn10Hz; 5773 USHORT usDVISSPercentage; 5774 USHORT usDVISSpreadRateIn10Hz; 5775 ULONG SclkDpmBoostMargin; 5776 ULONG SclkDpmThrottleMargin; 5777 USHORT SclkDpmTdpLimitPG; 5778 USHORT SclkDpmTdpLimitBoost; 5779 ULONG ulBoostEngineCLock; 5780 UCHAR ulBoostVid_2bit; 5781 UCHAR EnableBoost; 5782 USHORT GnbTdpLimit; 5783 USHORT usMaxLVDSPclkFreqInSingleLink; 5784 UCHAR ucLvdsMisc; 5785 UCHAR ucLVDSReserved; 5786 ULONG ulReserved3[15]; 5787 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5788}ATOM_INTEGRATED_SYSTEM_INFO_V6; 5789 5790// ulGPUCapInfo 5791#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5792#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5793 5794//ucLVDSMisc: 5795#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5796#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5797#define SYS_INFO_LVDSMISC__888_BPC 0x04 5798#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5799#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5800// new since Trinity 5801#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5802 5803// not used any more 5804#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5805#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5806 5807/********************************************************************************************************************** 5808 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5809ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5810ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5811ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5812sDISPCLK_Voltage: Report Display clock voltage requirement. 5813 5814ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5815 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5816 ATOM_DEVICE_CRT2_SUPPORT 0x0010 5817 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5818 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5819 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5820 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5821 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5822 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5823 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5824ulOtherDisplayMisc: Other display related flags, not defined yet. 5825ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5826 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5827 bit[3]=0: Enable HW AUX mode detection logic 5828 =1: Disable HW AUX mode dettion logic 5829ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5830 5831usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5832 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5833 5834 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5835 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5836 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5837 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5838 and enabling VariBri under the driver environment from PP table is optional. 5839 5840 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5841 that BL control from GPU is expected. 5842 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5843 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5844 it's per platform 5845 and enabling VariBri under the driver environment from PP table is optional. 5846 5847ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5848 Threshold on value to enter HTC_active state. 5849ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5850 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5851ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5852ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5853 =1: PCIE Power Gating Enabled 5854 Bit[1]=0: DDR-DLL shut-down feature disabled. 5855 1: DDR-DLL shut-down feature enabled. 5856 Bit[2]=0: DDR-PLL Power down feature disabled. 5857 1: DDR-PLL Power down feature enabled. 5858ulCPUCapInfo: TBD 5859usNBP0Voltage: VID for voltage on NB P0 State 5860usNBP1Voltage: VID for voltage on NB P1 State 5861usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5862usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5863usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5864 to indicate a range. 5865 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5866 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5867 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5868 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5869ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5870ucUMAChannelNumber: System memory channel numbers. 5871ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5872ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5873ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5874sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5875ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5876ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5877ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5878ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5879ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5880usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5881usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5882usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5883usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5884usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5885usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5886usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5887usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5888usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5889ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5890 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5891 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5892 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5893 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5894**********************************************************************************************************************/ 5895 5896// this Table is used for Liano/Ontario APU 5897typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5898{ 5899 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5900 ULONG ulPowerplayTable[128]; 5901}ATOM_FUSION_SYSTEM_INFO_V1; 5902 5903 5904typedef struct _ATOM_TDP_CONFIG_BITS 5905{ 5906#if ATOM_BIG_ENDIAN 5907 ULONG uReserved:2; 5908 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5909 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5910 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5911#else 5912 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5913 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5914 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5915 ULONG uReserved:2; 5916#endif 5917}ATOM_TDP_CONFIG_BITS; 5918 5919typedef union _ATOM_TDP_CONFIG 5920{ 5921 ATOM_TDP_CONFIG_BITS TDP_config; 5922 ULONG TDP_config_all; 5923}ATOM_TDP_CONFIG; 5924 5925/********************************************************************************************************************** 5926 ATOM_FUSION_SYSTEM_INFO_V1 Description 5927sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5928ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5929**********************************************************************************************************************/ 5930 5931// this IntegrateSystemInfoTable is used for Trinity APU 5932typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5933{ 5934 ATOM_COMMON_TABLE_HEADER sHeader; 5935 ULONG ulBootUpEngineClock; 5936 ULONG ulDentistVCOFreq; 5937 ULONG ulBootUpUMAClock; 5938 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5939 ULONG ulBootUpReqDisplayVector; 5940 ULONG ulOtherDisplayMisc; 5941 ULONG ulGPUCapInfo; 5942 ULONG ulSB_MMIO_Base_Addr; 5943 USHORT usRequestedPWMFreqInHz; 5944 UCHAR ucHtcTmpLmt; 5945 UCHAR ucHtcHystLmt; 5946 ULONG ulMinEngineClock; 5947 ULONG ulSystemConfig; 5948 ULONG ulCPUCapInfo; 5949 USHORT usNBP0Voltage; 5950 USHORT usNBP1Voltage; 5951 USHORT usBootUpNBVoltage; 5952 USHORT usExtDispConnInfoOffset; 5953 USHORT usPanelRefreshRateRange; 5954 UCHAR ucMemoryType; 5955 UCHAR ucUMAChannelNumber; 5956 UCHAR strVBIOSMsg[40]; 5957 ATOM_TDP_CONFIG asTdpConfig; 5958 ULONG ulReserved[19]; 5959 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5960 ULONG ulGMCRestoreResetTime; 5961 ULONG ulMinimumNClk; 5962 ULONG ulIdleNClk; 5963 ULONG ulDDR_DLL_PowerUpTime; 5964 ULONG ulDDR_PLL_PowerUpTime; 5965 USHORT usPCIEClkSSPercentage; 5966 USHORT usPCIEClkSSType; 5967 USHORT usLvdsSSPercentage; 5968 USHORT usLvdsSSpreadRateIn10Hz; 5969 USHORT usHDMISSPercentage; 5970 USHORT usHDMISSpreadRateIn10Hz; 5971 USHORT usDVISSPercentage; 5972 USHORT usDVISSpreadRateIn10Hz; 5973 ULONG SclkDpmBoostMargin; 5974 ULONG SclkDpmThrottleMargin; 5975 USHORT SclkDpmTdpLimitPG; 5976 USHORT SclkDpmTdpLimitBoost; 5977 ULONG ulBoostEngineCLock; 5978 UCHAR ulBoostVid_2bit; 5979 UCHAR EnableBoost; 5980 USHORT GnbTdpLimit; 5981 USHORT usMaxLVDSPclkFreqInSingleLink; 5982 UCHAR ucLvdsMisc; 5983 UCHAR ucTravisLVDSVolAdjust; 5984 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5985 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5986 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5987 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5988 UCHAR ucLVDSOffToOnDelay_in4Ms; 5989 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5990 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5991 UCHAR ucMinAllowedBL_Level; 5992 ULONG ulLCDBitDepthControlVal; 5993 ULONG ulNbpStateMemclkFreq[4]; 5994 USHORT usNBP2Voltage; 5995 USHORT usNBP3Voltage; 5996 ULONG ulNbpStateNClkFreq[4]; 5997 UCHAR ucNBDPMEnable; 5998 UCHAR ucReserved[3]; 5999 UCHAR ucDPMState0VclkFid; 6000 UCHAR ucDPMState0DclkFid; 6001 UCHAR ucDPMState1VclkFid; 6002 UCHAR ucDPMState1DclkFid; 6003 UCHAR ucDPMState2VclkFid; 6004 UCHAR ucDPMState2DclkFid; 6005 UCHAR ucDPMState3VclkFid; 6006 UCHAR ucDPMState3DclkFid; 6007 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6008}ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 6009 6010// ulOtherDisplayMisc 6011#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 6012#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 6013#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 6014#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 6015 6016// ulGPUCapInfo 6017#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 6018#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 6019#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 6020#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 6021//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6022#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 6023 6024//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 6025#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 6026 6027/********************************************************************************************************************** 6028 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 6029ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6030ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6031ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6032sDISPCLK_Voltage: Report Display clock voltage requirement. 6033 6034ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6035 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6036 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6037 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6038 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6039 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6040 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6041 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6042 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6043ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6044 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6045 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6046 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6047 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6048 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6049 bit[3]=0: VBIOS fast boot is disable 6050 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6051ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 6052 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 6053 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 6054 =1: DP mode use single PLL mode 6055 bit[3]=0: Enable AUX HW mode detection logic 6056 =1: Disable AUX HW mode detection logic 6057 6058ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 6059 6060usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6061 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6062 6063 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6064 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6065 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6066 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6067 and enabling VariBri under the driver environment from PP table is optional. 6068 6069 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6070 that BL control from GPU is expected. 6071 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6072 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6073 it's per platform 6074 and enabling VariBri under the driver environment from PP table is optional. 6075 6076ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 6077 Threshold on value to enter HTC_active state. 6078ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6079 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6080ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 6081ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6082 =1: PCIE Power Gating Enabled 6083 Bit[1]=0: DDR-DLL shut-down feature disabled. 6084 1: DDR-DLL shut-down feature enabled. 6085 Bit[2]=0: DDR-PLL Power down feature disabled. 6086 1: DDR-PLL Power down feature enabled. 6087ulCPUCapInfo: TBD 6088usNBP0Voltage: VID for voltage on NB P0 State 6089usNBP1Voltage: VID for voltage on NB P1 State 6090usNBP2Voltage: VID for voltage on NB P2 State 6091usNBP3Voltage: VID for voltage on NB P3 State 6092usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 6093usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6094usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6095 to indicate a range. 6096 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6097 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6098 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6099 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6100ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 6101ucUMAChannelNumber: System memory channel numbers. 6102ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 6103ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 6104ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 6105sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6106ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6107ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 6108ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 6109ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6110ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6111usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6112usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6113usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6114usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6115usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6116usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6117usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6118usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6119usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6120ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6121 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6122 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6123 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6124 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6125 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6126ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6127 value to program Travis register LVDS_CTRL_4 6128ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6129 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6130 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6131ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6132 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6133 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6134 6135ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6136 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6137 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6138 6139ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6140 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6141 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6142 6143ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6144 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6145 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6146 6147ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6148 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6149 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6150 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6151 6152ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6153 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6154 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6155 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6156 6157ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6158 6159ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 6160 6161**********************************************************************************************************************/ 6162 6163// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 6164typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 6165{ 6166 ATOM_COMMON_TABLE_HEADER sHeader; 6167 ULONG ulBootUpEngineClock; 6168 ULONG ulDentistVCOFreq; 6169 ULONG ulBootUpUMAClock; 6170 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 6171 ULONG ulBootUpReqDisplayVector; 6172 ULONG ulVBIOSMisc; 6173 ULONG ulGPUCapInfo; 6174 ULONG ulDISP_CLK2Freq; 6175 USHORT usRequestedPWMFreqInHz; 6176 UCHAR ucHtcTmpLmt; 6177 UCHAR ucHtcHystLmt; 6178 ULONG ulReserved2; 6179 ULONG ulSystemConfig; 6180 ULONG ulCPUCapInfo; 6181 ULONG ulReserved3; 6182 USHORT usGPUReservedSysMemSize; 6183 USHORT usExtDispConnInfoOffset; 6184 USHORT usPanelRefreshRateRange; 6185 UCHAR ucMemoryType; 6186 UCHAR ucUMAChannelNumber; 6187 UCHAR strVBIOSMsg[40]; 6188 ATOM_TDP_CONFIG asTdpConfig; 6189 ULONG ulReserved[19]; 6190 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 6191 ULONG ulGMCRestoreResetTime; 6192 ULONG ulReserved4; 6193 ULONG ulIdleNClk; 6194 ULONG ulDDR_DLL_PowerUpTime; 6195 ULONG ulDDR_PLL_PowerUpTime; 6196 USHORT usPCIEClkSSPercentage; 6197 USHORT usPCIEClkSSType; 6198 USHORT usLvdsSSPercentage; 6199 USHORT usLvdsSSpreadRateIn10Hz; 6200 USHORT usHDMISSPercentage; 6201 USHORT usHDMISSpreadRateIn10Hz; 6202 USHORT usDVISSPercentage; 6203 USHORT usDVISSpreadRateIn10Hz; 6204 ULONG ulGPUReservedSysMemBaseAddrLo; 6205 ULONG ulGPUReservedSysMemBaseAddrHi; 6206 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 6207 ULONG ulReserved5; 6208 USHORT usMaxLVDSPclkFreqInSingleLink; 6209 UCHAR ucLvdsMisc; 6210 UCHAR ucTravisLVDSVolAdjust; 6211 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6212 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6213 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6214 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6215 UCHAR ucLVDSOffToOnDelay_in4Ms; 6216 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6217 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6218 UCHAR ucMinAllowedBL_Level; 6219 ULONG ulLCDBitDepthControlVal; 6220 ULONG ulNbpStateMemclkFreq[4]; 6221 ULONG ulPSPVersion; 6222 ULONG ulNbpStateNClkFreq[4]; 6223 USHORT usNBPStateVoltage[4]; 6224 USHORT usBootUpNBVoltage; 6225 USHORT usReserved2; 6226 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6227}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 6228 6229/********************************************************************************************************************** 6230 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 6231ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6232ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6233ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6234sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 6235 6236ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6237 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6238 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6239 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6240 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6241 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6242 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6243 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6244 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6245 6246ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 6247 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6248 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6249 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6250 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6251 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6252 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6253 bit[3]=0: VBIOS fast boot is disable 6254 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6255 6256ulGPUCapInfo: bit[0~2]= Reserved 6257 bit[3]=0: Enable AUX HW mode detection logic 6258 =1: Disable AUX HW mode detection logic 6259 bit[4]=0: Disable DFS bypass feature 6260 =1: Enable DFS bypass feature 6261 6262usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6263 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6264 6265 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6266 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6267 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6268 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6269 and enabling VariBri under the driver environment from PP table is optional. 6270 6271 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6272 that BL control from GPU is expected. 6273 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6274 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6275 it's per platform 6276 and enabling VariBri under the driver environment from PP table is optional. 6277 6278ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 6279ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6280 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6281 6282ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6283 =1: PCIE Power Gating Enabled 6284 Bit[1]=0: DDR-DLL shut-down feature disabled. 6285 1: DDR-DLL shut-down feature enabled. 6286 Bit[2]=0: DDR-PLL Power down feature disabled. 6287 1: DDR-PLL Power down feature enabled. 6288 Bit[3]=0: GNB DPM is disabled 6289 =1: GNB DPM is enabled 6290ulCPUCapInfo: TBD 6291 6292usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6293usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6294 to indicate a range. 6295 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6296 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6297 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6298 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6299 6300ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 6301ucUMAChannelNumber: System memory channel numbers. 6302 6303strVBIOSMsg[40]: VBIOS boot up customized message string 6304 6305sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6306 6307ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6308ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 6309ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6310ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6311 6312usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6313usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6314usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6315usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6316usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6317usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6318usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6319usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6320 6321usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 6322ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 6323ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 6324 6325usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6326ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6327 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6328 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6329 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6330 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6331 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6332ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6333 value to program Travis register LVDS_CTRL_4 6334ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 6335 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6336 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6337 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6338ucLVDSPwrOnDEtoVARY_BL_in4Ms: 6339 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6340 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6341 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6342ucLVDSPwrOffVARY_BLtoDE_in4Ms: 6343 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6344 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6345 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6346ucLVDSPwrOffDEtoDIGON_in4Ms: 6347 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6348 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6349 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6350ucLVDSOffToOnDelay_in4Ms: 6351 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6352 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6353 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6354ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6355 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6356 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6357 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6358 6359ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6360 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6361 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6362 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6363ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6364 6365ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 6366 6367ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 6368ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 6369usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 6370usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 6371sExtDispConnInfo: Display connector information table provided to VBIOS 6372 6373**********************************************************************************************************************/ 6374 6375typedef struct _ATOM_I2C_REG_INFO 6376{ 6377 UCHAR ucI2cRegIndex; 6378 UCHAR ucI2cRegVal; 6379}ATOM_I2C_REG_INFO; 6380 6381// this IntegrateSystemInfoTable is used for Carrizo 6382typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 6383{ 6384 ATOM_COMMON_TABLE_HEADER sHeader; 6385 ULONG ulBootUpEngineClock; 6386 ULONG ulDentistVCOFreq; 6387 ULONG ulBootUpUMAClock; 6388 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 6389 ULONG ulBootUpReqDisplayVector; 6390 ULONG ulVBIOSMisc; 6391 ULONG ulGPUCapInfo; 6392 ULONG ulDISP_CLK2Freq; 6393 USHORT usRequestedPWMFreqInHz; 6394 UCHAR ucHtcTmpLmt; 6395 UCHAR ucHtcHystLmt; 6396 ULONG ulReserved2; 6397 ULONG ulSystemConfig; 6398 ULONG ulCPUCapInfo; 6399 ULONG ulReserved3; 6400 USHORT usGPUReservedSysMemSize; 6401 USHORT usExtDispConnInfoOffset; 6402 USHORT usPanelRefreshRateRange; 6403 UCHAR ucMemoryType; 6404 UCHAR ucUMAChannelNumber; 6405 UCHAR strVBIOSMsg[40]; 6406 ATOM_TDP_CONFIG asTdpConfig; 6407 UCHAR ucExtHDMIReDrvSlvAddr; 6408 UCHAR ucExtHDMIReDrvRegNum; 6409 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 6410 ULONG ulReserved[2]; 6411 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6412 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 6413 ULONG ulGMCRestoreResetTime; 6414 ULONG ulReserved4; 6415 ULONG ulIdleNClk; 6416 ULONG ulDDR_DLL_PowerUpTime; 6417 ULONG ulDDR_PLL_PowerUpTime; 6418 USHORT usPCIEClkSSPercentage; 6419 USHORT usPCIEClkSSType; 6420 USHORT usLvdsSSPercentage; 6421 USHORT usLvdsSSpreadRateIn10Hz; 6422 USHORT usHDMISSPercentage; 6423 USHORT usHDMISSpreadRateIn10Hz; 6424 USHORT usDVISSPercentage; 6425 USHORT usDVISSpreadRateIn10Hz; 6426 ULONG ulGPUReservedSysMemBaseAddrLo; 6427 ULONG ulGPUReservedSysMemBaseAddrHi; 6428 ULONG ulReserved5[3]; 6429 USHORT usMaxLVDSPclkFreqInSingleLink; 6430 UCHAR ucLvdsMisc; 6431 UCHAR ucTravisLVDSVolAdjust; 6432 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6433 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6434 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6435 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6436 UCHAR ucLVDSOffToOnDelay_in4Ms; 6437 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6438 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6439 UCHAR ucMinAllowedBL_Level; 6440 ULONG ulLCDBitDepthControlVal; 6441 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 6442 ULONG ulPSPVersion; 6443 ULONG ulNbpStateNClkFreq[4]; 6444 USHORT usNBPStateVoltage[4]; 6445 USHORT usBootUpNBVoltage; 6446 UCHAR ucEDPv1_4VSMode; 6447 UCHAR ucReserved2; 6448 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6449}ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 6450 6451 6452// definition for ucEDPv1_4VSMode 6453#define EDP_VS_LEGACY_MODE 0 6454#define EDP_VS_LOW_VDIFF_MODE 1 6455#define EDP_VS_HIGH_VDIFF_MODE 2 6456#define EDP_VS_STRETCH_MODE 3 6457#define EDP_VS_SINGLE_VDIFF_MODE 4 6458#define EDP_VS_VARIABLE_PREM_MODE 5 6459 6460 6461// ulGPUCapInfo 6462#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 6463#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10 6464//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6465#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 6466//ulGPUCapInfo[18]=1 indicate the IOMMU is not available 6467#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 6468//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. 6469#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000 6470 6471 6472typedef struct _DPHY_TIMING_PARA 6473{ 6474 UCHAR ucProfileID; // SENSOR_PROFILES 6475 ULONG ucPara; 6476} DPHY_TIMING_PARA; 6477 6478typedef struct _DPHY_ELEC_PARA 6479{ 6480 USHORT usPara[3]; 6481} DPHY_ELEC_PARA; 6482 6483typedef struct _CAMERA_MODULE_INFO 6484{ 6485 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user 6486 UCHAR strModuleName[8]; 6487 DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor 6488} CAMERA_MODULE_INFO; 6489 6490typedef struct _FLASHLIGHT_INFO 6491{ 6492 UCHAR ucID; // 0: Rear, 1: Front 6493 UCHAR strName[8]; 6494} FLASHLIGHT_INFO; 6495 6496typedef struct _CAMERA_DATA 6497{ 6498 ULONG ulVersionCode; 6499 CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max 6500 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max 6501 DPHY_ELEC_PARA asDphyElecPara; 6502 ULONG ulCrcVal; // CRC 6503}CAMERA_DATA; 6504 6505typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 6506{ 6507 ATOM_COMMON_TABLE_HEADER sHeader; 6508 ULONG ulBootUpEngineClock; 6509 ULONG ulDentistVCOFreq; 6510 ULONG ulBootUpUMAClock; 6511 ULONG ulReserved0[8]; 6512 ULONG ulBootUpReqDisplayVector; 6513 ULONG ulVBIOSMisc; 6514 ULONG ulGPUCapInfo; 6515 ULONG ulReserved1; 6516 USHORT usRequestedPWMFreqInHz; 6517 UCHAR ucHtcTmpLmt; 6518 UCHAR ucHtcHystLmt; 6519 ULONG ulReserved2; 6520 ULONG ulSystemConfig; 6521 ULONG ulCPUCapInfo; 6522 ULONG ulReserved3; 6523 USHORT usGPUReservedSysMemSize; 6524 USHORT usExtDispConnInfoOffset; 6525 USHORT usPanelRefreshRateRange; 6526 UCHAR ucMemoryType; 6527 UCHAR ucUMAChannelNumber; 6528 ULONG ulMsgReserved[10]; 6529 ATOM_TDP_CONFIG asTdpConfig; 6530 ULONG ulReserved[7]; 6531 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6532 ULONG ulReserved6[10]; 6533 ULONG ulGMCRestoreResetTime; 6534 ULONG ulReserved4; 6535 ULONG ulIdleNClk; 6536 ULONG ulDDR_DLL_PowerUpTime; 6537 ULONG ulDDR_PLL_PowerUpTime; 6538 USHORT usPCIEClkSSPercentage; 6539 USHORT usPCIEClkSSType; 6540 USHORT usLvdsSSPercentage; 6541 USHORT usLvdsSSpreadRateIn10Hz; 6542 USHORT usHDMISSPercentage; 6543 USHORT usHDMISSpreadRateIn10Hz; 6544 USHORT usDVISSPercentage; 6545 USHORT usDVISSpreadRateIn10Hz; 6546 ULONG ulGPUReservedSysMemBaseAddrLo; 6547 ULONG ulGPUReservedSysMemBaseAddrHi; 6548 ULONG ulReserved5[3]; 6549 USHORT usMaxLVDSPclkFreqInSingleLink; 6550 UCHAR ucLvdsMisc; 6551 UCHAR ucTravisLVDSVolAdjust; 6552 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6553 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6554 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6555 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6556 UCHAR ucLVDSOffToOnDelay_in4Ms; 6557 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6558 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6559 UCHAR ucMinAllowedBL_Level; 6560 ULONG ulLCDBitDepthControlVal; 6561 ULONG ulNbpStateMemclkFreq[2]; 6562 ULONG ulReserved7[2]; 6563 ULONG ulPSPVersion; 6564 ULONG ulNbpStateNClkFreq[4]; 6565 USHORT usNBPStateVoltage[4]; 6566 USHORT usBootUpNBVoltage; 6567 UCHAR ucEDPv1_4VSMode; 6568 UCHAR ucReserved2; 6569 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6570 CAMERA_DATA asCameraInfo; 6571 ULONG ulReserved8[29]; 6572}ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 6573 6574 6575// this Table is used for Kaveri/Kabini APU 6576typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 6577{ 6578 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6579 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 6580}ATOM_FUSION_SYSTEM_INFO_V2; 6581 6582 6583typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 6584{ 6585 ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6586 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable 6587}ATOM_FUSION_SYSTEM_INFO_V3; 6588 6589#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800 6590 6591/**************************************************************************/ 6592// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 6593//Memory SS Info Table 6594//Define Memory Clock SS chip ID 6595#define ICS91719 1 6596#define ICS91720 2 6597 6598//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 6599typedef struct _ATOM_I2C_DATA_RECORD 6600{ 6601 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 6602 UCHAR ucI2CData[]; //I2C data in bytes, should be less than 16 bytes usually 6603}ATOM_I2C_DATA_RECORD; 6604 6605 6606//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 6607typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 6608{ 6609 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 6610 UCHAR ucSSChipID; //SS chip being used 6611 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 6612 UCHAR ucNumOfI2CDataRecords; //number of data block 6613 ATOM_I2C_DATA_RECORD asI2CData[]; 6614}ATOM_I2C_DEVICE_SETUP_INFO; 6615 6616//========================================================================================== 6617typedef struct _ATOM_ASIC_MVDD_INFO 6618{ 6619 ATOM_COMMON_TABLE_HEADER sHeader; 6620 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[]; 6621}ATOM_ASIC_MVDD_INFO; 6622 6623//========================================================================================== 6624#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 6625 6626//========================================================================================== 6627/**************************************************************************/ 6628 6629typedef struct _ATOM_ASIC_SS_ASSIGNMENT 6630{ 6631 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 6632 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6633 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 6634 UCHAR ucClockIndication; //Indicate which clock source needs SS 6635 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 6636 UCHAR ucReserved[2]; 6637}ATOM_ASIC_SS_ASSIGNMENT; 6638 6639//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 6640//SS is not required or enabled if a match is not found. 6641#define ASIC_INTERNAL_MEMORY_SS 1 6642#define ASIC_INTERNAL_ENGINE_SS 2 6643#define ASIC_INTERNAL_UVD_SS 3 6644#define ASIC_INTERNAL_SS_ON_TMDS 4 6645#define ASIC_INTERNAL_SS_ON_HDMI 5 6646#define ASIC_INTERNAL_SS_ON_LVDS 6 6647#define ASIC_INTERNAL_SS_ON_DP 7 6648#define ASIC_INTERNAL_SS_ON_DCPLL 8 6649#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 6650#define ASIC_INTERNAL_VCE_SS 10 6651#define ASIC_INTERNAL_GPUPLL_SS 11 6652 6653 6654typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 6655{ 6656 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6657 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6658 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6659 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6660 UCHAR ucClockIndication; //Indicate which clock source needs SS 6661 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6662 UCHAR ucReserved[2]; 6663}ATOM_ASIC_SS_ASSIGNMENT_V2; 6664 6665//ucSpreadSpectrumMode 6666//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 6667//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 6668//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 6669//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 6670//#define ATOM_INTERNAL_SS_MASK 0x00000000 6671//#define ATOM_EXTERNAL_SS_MASK 0x00000002 6672 6673typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 6674{ 6675 ATOM_COMMON_TABLE_HEADER sHeader; 6676 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 6677}ATOM_ASIC_INTERNAL_SS_INFO; 6678 6679typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 6680{ 6681 ATOM_COMMON_TABLE_HEADER sHeader; 6682 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[]; //this is point only. 6683}ATOM_ASIC_INTERNAL_SS_INFO_V2; 6684 6685typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 6686{ 6687 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6688 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6689 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 6690 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6691 UCHAR ucClockIndication; //Indicate which clock source needs SS 6692 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6693 UCHAR ucReserved[2]; 6694}ATOM_ASIC_SS_ASSIGNMENT_V3; 6695 6696//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 6697#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 6698#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 6699#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 6700 6701typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 6702{ 6703 ATOM_COMMON_TABLE_HEADER sHeader; 6704 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[]; //this is pointer only. 6705}ATOM_ASIC_INTERNAL_SS_INFO_V3; 6706 6707 6708//==============================Scratch Pad Definition Portion=============================== 6709#define ATOM_DEVICE_CONNECT_INFO_DEF 0 6710#define ATOM_ROM_LOCATION_DEF 1 6711#define ATOM_TV_STANDARD_DEF 2 6712#define ATOM_ACTIVE_INFO_DEF 3 6713#define ATOM_LCD_INFO_DEF 4 6714#define ATOM_DOS_REQ_INFO_DEF 5 6715#define ATOM_ACC_CHANGE_INFO_DEF 6 6716#define ATOM_DOS_MODE_INFO_DEF 7 6717#define ATOM_I2C_CHANNEL_STATUS_DEF 8 6718#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 6719#define ATOM_INTERNAL_TIMER_DEF 10 6720 6721// BIOS_0_SCRATCH Definition 6722#define ATOM_S0_CRT1_MONO 0x00000001L 6723#define ATOM_S0_CRT1_COLOR 0x00000002L 6724#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 6725 6726#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 6727#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 6728#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 6729 6730#define ATOM_S0_CV_A 0x00000010L 6731#define ATOM_S0_CV_DIN_A 0x00000020L 6732#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 6733 6734 6735#define ATOM_S0_CRT2_MONO 0x00000100L 6736#define ATOM_S0_CRT2_COLOR 0x00000200L 6737#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6738 6739#define ATOM_S0_TV1_COMPOSITE 0x00000400L 6740#define ATOM_S0_TV1_SVIDEO 0x00000800L 6741#define ATOM_S0_TV1_SCART 0x00004000L 6742#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6743 6744#define ATOM_S0_CV 0x00001000L 6745#define ATOM_S0_CV_DIN 0x00002000L 6746#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6747 6748#define ATOM_S0_DFP1 0x00010000L 6749#define ATOM_S0_DFP2 0x00020000L 6750#define ATOM_S0_LCD1 0x00040000L 6751#define ATOM_S0_LCD2 0x00080000L 6752#define ATOM_S0_DFP6 0x00100000L 6753#define ATOM_S0_DFP3 0x00200000L 6754#define ATOM_S0_DFP4 0x00400000L 6755#define ATOM_S0_DFP5 0x00800000L 6756 6757 6758#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6759 6760#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6761 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6762 6763#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6764#define ATOM_S0_THERMAL_STATE_SHIFT 26 6765 6766#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6767#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6768 6769#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6770#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6771#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6772#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6773 6774//Byte aligned defintion for BIOS usage 6775#define ATOM_S0_CRT1_MONOb0 0x01 6776#define ATOM_S0_CRT1_COLORb0 0x02 6777#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6778 6779#define ATOM_S0_TV1_COMPOSITEb0 0x04 6780#define ATOM_S0_TV1_SVIDEOb0 0x08 6781#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6782 6783#define ATOM_S0_CVb0 0x10 6784#define ATOM_S0_CV_DINb0 0x20 6785#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6786 6787#define ATOM_S0_CRT2_MONOb1 0x01 6788#define ATOM_S0_CRT2_COLORb1 0x02 6789#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6790 6791#define ATOM_S0_TV1_COMPOSITEb1 0x04 6792#define ATOM_S0_TV1_SVIDEOb1 0x08 6793#define ATOM_S0_TV1_SCARTb1 0x40 6794#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6795 6796#define ATOM_S0_CVb1 0x10 6797#define ATOM_S0_CV_DINb1 0x20 6798#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6799 6800#define ATOM_S0_DFP1b2 0x01 6801#define ATOM_S0_DFP2b2 0x02 6802#define ATOM_S0_LCD1b2 0x04 6803#define ATOM_S0_LCD2b2 0x08 6804#define ATOM_S0_DFP6b2 0x10 6805#define ATOM_S0_DFP3b2 0x20 6806#define ATOM_S0_DFP4b2 0x40 6807#define ATOM_S0_DFP5b2 0x80 6808 6809 6810#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6811#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6812 6813#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6814#define ATOM_S0_LCD1_SHIFT 18 6815 6816// BIOS_1_SCRATCH Definition 6817#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6818#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6819 6820// BIOS_2_SCRATCH Definition 6821#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6822#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6823#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6824 6825#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6826#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6827#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6828 6829#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6830#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6831 6832#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6833#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6834#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6835#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6836#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6837#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6838 6839 6840//Byte aligned defintion for BIOS usage 6841#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6842#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6843#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6844 6845#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6846#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6847#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6848 6849 6850// BIOS_3_SCRATCH Definition 6851#define ATOM_S3_CRT1_ACTIVE 0x00000001L 6852#define ATOM_S3_LCD1_ACTIVE 0x00000002L 6853#define ATOM_S3_TV1_ACTIVE 0x00000004L 6854#define ATOM_S3_DFP1_ACTIVE 0x00000008L 6855#define ATOM_S3_CRT2_ACTIVE 0x00000010L 6856#define ATOM_S3_LCD2_ACTIVE 0x00000020L 6857#define ATOM_S3_DFP6_ACTIVE 0x00000040L 6858#define ATOM_S3_DFP2_ACTIVE 0x00000080L 6859#define ATOM_S3_CV_ACTIVE 0x00000100L 6860#define ATOM_S3_DFP3_ACTIVE 0x00000200L 6861#define ATOM_S3_DFP4_ACTIVE 0x00000400L 6862#define ATOM_S3_DFP5_ACTIVE 0x00000800L 6863 6864 6865#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6866 6867#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6868#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6869 6870#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6871#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6872#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6873#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6874#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6875#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6876#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6877#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6878#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6879#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6880#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6881#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6882 6883 6884#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6885#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6886//Below two definitions are not supported in pplib, but in the old powerplay in DAL 6887#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6888#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6889 6890 6891 6892//Byte aligned defintion for BIOS usage 6893#define ATOM_S3_CRT1_ACTIVEb0 0x01 6894#define ATOM_S3_LCD1_ACTIVEb0 0x02 6895#define ATOM_S3_TV1_ACTIVEb0 0x04 6896#define ATOM_S3_DFP1_ACTIVEb0 0x08 6897#define ATOM_S3_CRT2_ACTIVEb0 0x10 6898#define ATOM_S3_LCD2_ACTIVEb0 0x20 6899#define ATOM_S3_DFP6_ACTIVEb0 0x40 6900#define ATOM_S3_DFP2_ACTIVEb0 0x80 6901#define ATOM_S3_CV_ACTIVEb1 0x01 6902#define ATOM_S3_DFP3_ACTIVEb1 0x02 6903#define ATOM_S3_DFP4_ACTIVEb1 0x04 6904#define ATOM_S3_DFP5_ACTIVEb1 0x08 6905 6906 6907#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6908 6909#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6910#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6911#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6912#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6913#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6914#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6915#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6916#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6917#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6918#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6919#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6920#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6921 6922 6923#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6924 6925 6926// BIOS_4_SCRATCH Definition 6927#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6928#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6929#define ATOM_S4_LCD1_REFRESH_SHIFT 8 6930 6931//Byte aligned defintion for BIOS usage 6932#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6933#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6934#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6935 6936// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6937#define ATOM_S5_DOS_REQ_CRT1b0 0x01 6938#define ATOM_S5_DOS_REQ_LCD1b0 0x02 6939#define ATOM_S5_DOS_REQ_TV1b0 0x04 6940#define ATOM_S5_DOS_REQ_DFP1b0 0x08 6941#define ATOM_S5_DOS_REQ_CRT2b0 0x10 6942#define ATOM_S5_DOS_REQ_LCD2b0 0x20 6943#define ATOM_S5_DOS_REQ_DFP6b0 0x40 6944#define ATOM_S5_DOS_REQ_DFP2b0 0x80 6945#define ATOM_S5_DOS_REQ_CVb1 0x01 6946#define ATOM_S5_DOS_REQ_DFP3b1 0x02 6947#define ATOM_S5_DOS_REQ_DFP4b1 0x04 6948#define ATOM_S5_DOS_REQ_DFP5b1 0x08 6949 6950 6951#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6952 6953#define ATOM_S5_DOS_REQ_CRT1 0x0001 6954#define ATOM_S5_DOS_REQ_LCD1 0x0002 6955#define ATOM_S5_DOS_REQ_TV1 0x0004 6956#define ATOM_S5_DOS_REQ_DFP1 0x0008 6957#define ATOM_S5_DOS_REQ_CRT2 0x0010 6958#define ATOM_S5_DOS_REQ_LCD2 0x0020 6959#define ATOM_S5_DOS_REQ_DFP6 0x0040 6960#define ATOM_S5_DOS_REQ_DFP2 0x0080 6961#define ATOM_S5_DOS_REQ_CV 0x0100 6962#define ATOM_S5_DOS_REQ_DFP3 0x0200 6963#define ATOM_S5_DOS_REQ_DFP4 0x0400 6964#define ATOM_S5_DOS_REQ_DFP5 0x0800 6965 6966#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6967#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6968#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6969#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6970#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6971 (ATOM_S5_DOS_FORCE_CVb3<<8)) 6972// BIOS_6_SCRATCH Definition 6973#define ATOM_S6_DEVICE_CHANGE 0x00000001L 6974#define ATOM_S6_SCALER_CHANGE 0x00000002L 6975#define ATOM_S6_LID_CHANGE 0x00000004L 6976#define ATOM_S6_DOCKING_CHANGE 0x00000008L 6977#define ATOM_S6_ACC_MODE 0x00000010L 6978#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6979#define ATOM_S6_LID_STATE 0x00000040L 6980#define ATOM_S6_DOCK_STATE 0x00000080L 6981#define ATOM_S6_CRITICAL_STATE 0x00000100L 6982#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6983#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6984#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6985#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6986#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6987 6988#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6989#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6990 6991#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6992#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6993#define ATOM_S6_ACC_REQ_TV1 0x00040000L 6994#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6995#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6996#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 6997#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 6998#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 6999#define ATOM_S6_ACC_REQ_CV 0x01000000L 7000#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 7001#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 7002#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 7003 7004#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 7005#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 7006#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 7007#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 7008#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 7009 7010//Byte aligned defintion for BIOS usage 7011#define ATOM_S6_DEVICE_CHANGEb0 0x01 7012#define ATOM_S6_SCALER_CHANGEb0 0x02 7013#define ATOM_S6_LID_CHANGEb0 0x04 7014#define ATOM_S6_DOCKING_CHANGEb0 0x08 7015#define ATOM_S6_ACC_MODEb0 0x10 7016#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 7017#define ATOM_S6_LID_STATEb0 0x40 7018#define ATOM_S6_DOCK_STATEb0 0x80 7019#define ATOM_S6_CRITICAL_STATEb1 0x01 7020#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 7021#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 7022#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 7023#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 7024#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 7025 7026#define ATOM_S6_ACC_REQ_CRT1b2 0x01 7027#define ATOM_S6_ACC_REQ_LCD1b2 0x02 7028#define ATOM_S6_ACC_REQ_TV1b2 0x04 7029#define ATOM_S6_ACC_REQ_DFP1b2 0x08 7030#define ATOM_S6_ACC_REQ_CRT2b2 0x10 7031#define ATOM_S6_ACC_REQ_LCD2b2 0x20 7032#define ATOM_S6_ACC_REQ_DFP6b2 0x40 7033#define ATOM_S6_ACC_REQ_DFP2b2 0x80 7034#define ATOM_S6_ACC_REQ_CVb3 0x01 7035#define ATOM_S6_ACC_REQ_DFP3b3 0x02 7036#define ATOM_S6_ACC_REQ_DFP4b3 0x04 7037#define ATOM_S6_ACC_REQ_DFP5b3 0x08 7038 7039#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 7040#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 7041#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 7042#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 7043#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 7044 7045#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 7046#define ATOM_S6_SCALER_CHANGE_SHIFT 1 7047#define ATOM_S6_LID_CHANGE_SHIFT 2 7048#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 7049#define ATOM_S6_ACC_MODE_SHIFT 4 7050#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 7051#define ATOM_S6_LID_STATE_SHIFT 6 7052#define ATOM_S6_DOCK_STATE_SHIFT 7 7053#define ATOM_S6_CRITICAL_STATE_SHIFT 8 7054#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 7055#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 7056#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 7057#define ATOM_S6_REQ_SCALER_SHIFT 12 7058#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 7059#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 7060#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 7061#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 7062#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 7063#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 7064#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 7065 7066// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 7067#define ATOM_S7_DOS_MODE_TYPEb0 0x03 7068#define ATOM_S7_DOS_MODE_VGAb0 0x00 7069#define ATOM_S7_DOS_MODE_VESAb0 0x01 7070#define ATOM_S7_DOS_MODE_EXTb0 0x02 7071#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 7072#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 7073#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 7074#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 7075#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 7076#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 7077 7078#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 7079 7080// BIOS_8_SCRATCH Definition 7081#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 7082#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 7083 7084#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 7085#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 7086 7087// BIOS_9_SCRATCH Definition 7088#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 7089#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 7090#endif 7091#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 7092#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 7093#endif 7094#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 7095#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 7096#endif 7097#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 7098#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 7099#endif 7100 7101 7102#define ATOM_FLAG_SET 0x20 7103#define ATOM_FLAG_CLEAR 0 7104#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 7105#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 7106#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 7107#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 7108#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 7109 7110#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 7111#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 7112 7113#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 7114#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 7115#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 7116 7117#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 7118#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 7119#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 7120 7121#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 7122#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 7123 7124#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 7125#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 7126 7127#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 7128#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 7129 7130#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7131 7132#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7133 7134#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 7135#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 7136#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 7137#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 7138 7139/****************************************************************************/ 7140//Portion II: Definitinos only used in Driver 7141/****************************************************************************/ 7142 7143// Macros used by driver 7144 7145#ifdef __cplusplus 7146#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 7147 7148#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 7149#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 7150#else // not __cplusplus 7151#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / sizeof(USHORT)) 7152 7153#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 7154#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 7155#endif // __cplusplus 7156 7157#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 7158#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 7159 7160/****************************************************************************/ 7161//Portion III: Definitinos only used in VBIOS 7162/****************************************************************************/ 7163#define ATOM_DAC_SRC 0x80 7164#define ATOM_SRC_DAC1 0 7165#define ATOM_SRC_DAC2 0x80 7166 7167 7168 7169typedef struct _MEMORY_PLLINIT_PARAMETERS 7170{ 7171 ULONG ulTargetMemoryClock; //In 10Khz unit 7172 UCHAR ucAction; //not define yet 7173 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 7174 UCHAR ucFbDiv; //FB value 7175 UCHAR ucPostDiv; //Post div 7176}MEMORY_PLLINIT_PARAMETERS; 7177 7178#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 7179 7180 7181#define GPIO_PIN_WRITE 0x01 7182#define GPIO_PIN_READ 0x00 7183 7184typedef struct _GPIO_PIN_CONTROL_PARAMETERS 7185{ 7186 UCHAR ucGPIO_ID; //return value, read from GPIO pins 7187 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 7188 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 7189 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 7190}GPIO_PIN_CONTROL_PARAMETERS; 7191 7192typedef struct _ENABLE_SCALER_PARAMETERS 7193{ 7194 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 7195 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 7196 UCHAR ucTVStandard; // 7197 UCHAR ucPadding[1]; 7198}ENABLE_SCALER_PARAMETERS; 7199#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 7200 7201//ucEnable: 7202#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 7203#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 7204#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 7205#define SCALER_ENABLE_MULTITAP_MODE 3 7206 7207typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 7208{ 7209 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 7210 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 7211 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 7212 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 7213 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7214}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 7215 7216typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 7217{ 7218 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 7219 ENABLE_CRTC_PARAMETERS sReserved; 7220}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 7221 7222typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 7223{ 7224 USHORT usHight; // Image Hight 7225 USHORT usWidth; // Image Width 7226 UCHAR ucSurface; // Surface 1 or 2 7227 UCHAR ucPadding[3]; 7228}ENABLE_GRAPH_SURFACE_PARAMETERS; 7229 7230typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 7231{ 7232 USHORT usHight; // Image Hight 7233 USHORT usWidth; // Image Width 7234 UCHAR ucSurface; // Surface 1 or 2 7235 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7236 UCHAR ucPadding[2]; 7237}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 7238 7239typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 7240{ 7241 USHORT usHight; // Image Hight 7242 USHORT usWidth; // Image Width 7243 UCHAR ucSurface; // Surface 1 or 2 7244 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7245 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 7246}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 7247 7248typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 7249{ 7250 USHORT usHight; // Image Hight 7251 USHORT usWidth; // Image Width 7252 USHORT usGraphPitch; 7253 UCHAR ucColorDepth; 7254 UCHAR ucPixelFormat; 7255 UCHAR ucSurface; // Surface 1 or 2 7256 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7257 UCHAR ucModeType; 7258 UCHAR ucReserved; 7259}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 7260 7261// ucEnable 7262#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 7263#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 7264 7265typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 7266{ 7267 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 7268 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 7269}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 7270 7271typedef struct _MEMORY_CLEAN_UP_PARAMETERS 7272{ 7273 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 7274 USHORT usMemorySize; //8Kb blocks aligned 7275}MEMORY_CLEAN_UP_PARAMETERS; 7276 7277#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 7278 7279typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 7280{ 7281 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7282 USHORT usY_Size; 7283}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 7284 7285typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 7286{ 7287 union{ 7288 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7289 USHORT usSurface; 7290 }; 7291 USHORT usY_Size; 7292 USHORT usDispXStart; 7293 USHORT usDispYStart; 7294}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 7295 7296 7297typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 7298{ 7299 UCHAR ucLutId; 7300 UCHAR ucAction; 7301 USHORT usLutStartIndex; 7302 USHORT usLutLength; 7303 USHORT usLutOffsetInVram; 7304}PALETTE_DATA_CONTROL_PARAMETERS_V3; 7305 7306// ucAction: 7307#define PALETTE_DATA_AUTO_FILL 1 7308#define PALETTE_DATA_READ 2 7309#define PALETTE_DATA_WRITE 3 7310 7311 7312typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 7313{ 7314 UCHAR ucInterruptId; 7315 UCHAR ucServiceId; 7316 UCHAR ucStatus; 7317 UCHAR ucReserved; 7318}INTERRUPT_SERVICE_PARAMETER_V2; 7319 7320// ucInterruptId 7321#define HDP1_INTERRUPT_ID 1 7322#define HDP2_INTERRUPT_ID 2 7323#define HDP3_INTERRUPT_ID 3 7324#define HDP4_INTERRUPT_ID 4 7325#define HDP5_INTERRUPT_ID 5 7326#define HDP6_INTERRUPT_ID 6 7327#define SW_INTERRUPT_ID 11 7328 7329// ucAction 7330#define INTERRUPT_SERVICE_GEN_SW_INT 1 7331#define INTERRUPT_SERVICE_GET_STATUS 2 7332 7333 // ucStatus 7334#define INTERRUPT_STATUS__INT_TRIGGER 1 7335#define INTERRUPT_STATUS__HPD_HIGH 2 7336 7337typedef struct _EFUSE_INPUT_PARAMETER 7338{ 7339 USHORT usEfuseIndex; 7340 UCHAR ucBitShift; 7341 UCHAR ucBitLength; 7342}EFUSE_INPUT_PARAMETER; 7343 7344// ReadEfuseValue command table input/output parameter 7345typedef union _READ_EFUSE_VALUE_PARAMETER 7346{ 7347 EFUSE_INPUT_PARAMETER sEfuse; 7348 ULONG ulEfuseValue; 7349}READ_EFUSE_VALUE_PARAMETER; 7350 7351typedef struct _INDIRECT_IO_ACCESS 7352{ 7353 ATOM_COMMON_TABLE_HEADER sHeader; 7354 UCHAR IOAccessSequence[256]; 7355} INDIRECT_IO_ACCESS; 7356 7357#define INDIRECT_READ 0x00 7358#define INDIRECT_WRITE 0x80 7359 7360#define INDIRECT_IO_MM 0 7361#define INDIRECT_IO_PLL 1 7362#define INDIRECT_IO_MC 2 7363#define INDIRECT_IO_PCIE 3 7364#define INDIRECT_IO_PCIEP 4 7365#define INDIRECT_IO_NBMISC 5 7366#define INDIRECT_IO_SMU 5 7367 7368#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 7369#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 7370#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 7371#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 7372#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 7373#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 7374#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 7375#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 7376#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 7377#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 7378#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 7379#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 7380 7381 7382typedef struct _ATOM_OEM_INFO 7383{ 7384 ATOM_COMMON_TABLE_HEADER sHeader; 7385 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7386}ATOM_OEM_INFO; 7387 7388typedef struct _ATOM_TV_MODE 7389{ 7390 UCHAR ucVMode_Num; //Video mode number 7391 UCHAR ucTV_Mode_Num; //Internal TV mode number 7392}ATOM_TV_MODE; 7393 7394typedef struct _ATOM_BIOS_INT_TVSTD_MODE 7395{ 7396 ATOM_COMMON_TABLE_HEADER sHeader; 7397 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 7398 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 7399 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 7400 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7401 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7402}ATOM_BIOS_INT_TVSTD_MODE; 7403 7404 7405typedef struct _ATOM_TV_MODE_SCALER_PTR 7406{ 7407 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 7408 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 7409 UCHAR ucTV_Mode_Num; 7410}ATOM_TV_MODE_SCALER_PTR; 7411 7412typedef struct _ATOM_STANDARD_VESA_TIMING 7413{ 7414 ATOM_COMMON_TABLE_HEADER sHeader; 7415 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 7416}ATOM_STANDARD_VESA_TIMING; 7417 7418 7419typedef struct _ATOM_STD_FORMAT 7420{ 7421 USHORT usSTD_HDisp; 7422 USHORT usSTD_VDisp; 7423 USHORT usSTD_RefreshRate; 7424 USHORT usReserved; 7425}ATOM_STD_FORMAT; 7426 7427typedef struct _ATOM_VESA_TO_EXTENDED_MODE 7428{ 7429 USHORT usVESA_ModeNumber; 7430 USHORT usExtendedModeNumber; 7431}ATOM_VESA_TO_EXTENDED_MODE; 7432 7433typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 7434{ 7435 ATOM_COMMON_TABLE_HEADER sHeader; 7436 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 7437}ATOM_VESA_TO_INTENAL_MODE_LUT; 7438 7439/*************** ATOM Memory Related Data Structure ***********************/ 7440typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 7441 UCHAR ucMemoryType; 7442 UCHAR ucMemoryVendor; 7443 UCHAR ucAdjMCId; 7444 UCHAR ucDynClkId; 7445 ULONG ulDllResetClkRange; 7446}ATOM_MEMORY_VENDOR_BLOCK; 7447 7448 7449typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 7450#if ATOM_BIG_ENDIAN 7451 ULONG ucMemBlkId:8; 7452 ULONG ulMemClockRange:24; 7453#else 7454 ULONG ulMemClockRange:24; 7455 ULONG ucMemBlkId:8; 7456#endif 7457}ATOM_MEMORY_SETTING_ID_CONFIG; 7458 7459typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 7460{ 7461 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 7462 ULONG ulAccess; 7463}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 7464 7465 7466typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 7467 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 7468 ULONG aulMemData[1]; 7469}ATOM_MEMORY_SETTING_DATA_BLOCK; 7470 7471 7472typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 7473 USHORT usRegIndex; // MC register index 7474 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 7475}ATOM_INIT_REG_INDEX_FORMAT; 7476 7477 7478typedef struct _ATOM_INIT_REG_BLOCK{ 7479 USHORT usRegIndexTblSize; //size of asRegIndexBuf 7480 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 7481 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 7482 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 7483}ATOM_INIT_REG_BLOCK; 7484 7485#define END_OF_REG_INDEX_BLOCK 0x0ffff 7486#define END_OF_REG_DATA_BLOCK 0x00000000 7487#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 7488#define CLOCK_RANGE_HIGHEST 0x00ffffff 7489 7490#define VALUE_DWORD SIZEOF ULONG 7491#define VALUE_SAME_AS_ABOVE 0 7492#define VALUE_MASK_DWORD 0x84 7493 7494#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 7495#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 7496#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 7497//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 7498#define ACCESS_PLACEHOLDER 0x80 7499 7500 7501typedef struct _ATOM_MC_INIT_PARAM_TABLE 7502{ 7503 ATOM_COMMON_TABLE_HEADER sHeader; 7504 USHORT usAdjustARB_SEQDataOffset; 7505 USHORT usMCInitMemTypeTblOffset; 7506 USHORT usMCInitCommonTblOffset; 7507 USHORT usMCInitPowerDownTblOffset; 7508 ULONG ulARB_SEQDataBuf[32]; 7509 ATOM_INIT_REG_BLOCK asMCInitMemType; 7510 ATOM_INIT_REG_BLOCK asMCInitCommon; 7511}ATOM_MC_INIT_PARAM_TABLE; 7512 7513 7514typedef struct _ATOM_REG_INIT_SETTING 7515{ 7516 USHORT usRegIndex; 7517 ULONG ulRegValue; 7518}ATOM_REG_INIT_SETTING; 7519 7520typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 7521{ 7522 ATOM_COMMON_TABLE_HEADER sHeader; 7523 ULONG ulMCUcodeVersion; 7524 ULONG ulMCUcodeRomStartAddr; 7525 ULONG ulMCUcodeLength; 7526 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 7527 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 7528}ATOM_MC_INIT_PARAM_TABLE_V2_1; 7529 7530 7531#define _4Mx16 0x2 7532#define _4Mx32 0x3 7533#define _8Mx16 0x12 7534#define _8Mx32 0x13 7535#define _8Mx128 0x15 7536#define _16Mx16 0x22 7537#define _16Mx32 0x23 7538#define _16Mx128 0x25 7539#define _32Mx16 0x32 7540#define _32Mx32 0x33 7541#define _32Mx128 0x35 7542#define _64Mx8 0x41 7543#define _64Mx16 0x42 7544#define _64Mx32 0x43 7545#define _64Mx128 0x45 7546#define _128Mx8 0x51 7547#define _128Mx16 0x52 7548#define _128Mx32 0x53 7549#define _256Mx8 0x61 7550#define _256Mx16 0x62 7551#define _256Mx32 0x63 7552#define _512Mx8 0x71 7553#define _512Mx16 0x72 7554 7555 7556#define SAMSUNG 0x1 7557#define INFINEON 0x2 7558#define ELPIDA 0x3 7559#define ETRON 0x4 7560#define NANYA 0x5 7561#define HYNIX 0x6 7562#define MOSEL 0x7 7563#define WINBOND 0x8 7564#define ESMT 0x9 7565#define MICRON 0xF 7566 7567#define QIMONDA INFINEON 7568#define PROMOS MOSEL 7569#define KRETON INFINEON 7570#define ELIXIR NANYA 7571#define MEZZA ELPIDA 7572 7573 7574/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 7575 7576#define UCODE_ROM_START_ADDRESS 0x1b800 7577#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 7578 7579//uCode block header for reference 7580 7581typedef struct _MCuCodeHeader 7582{ 7583 ULONG ulSignature; 7584 UCHAR ucRevision; 7585 UCHAR ucChecksum; 7586 UCHAR ucReserved1; 7587 UCHAR ucReserved2; 7588 USHORT usParametersLength; 7589 USHORT usUCodeLength; 7590 USHORT usReserved1; 7591 USHORT usReserved2; 7592} MCuCodeHeader; 7593 7594////////////////////////////////////////////////////////////////////////////////// 7595 7596#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 7597 7598#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 7599typedef struct _ATOM_VRAM_MODULE_V1 7600{ 7601 ULONG ulReserved; 7602 USHORT usEMRSValue; 7603 USHORT usMRSValue; 7604 USHORT usReserved; 7605 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7606 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 7607 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 7608 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7609 UCHAR ucRow; // Number of Row,in power of 2; 7610 UCHAR ucColumn; // Number of Column,in power of 2; 7611 UCHAR ucBank; // Nunber of Bank; 7612 UCHAR ucRank; // Number of Rank, in power of 2 7613 UCHAR ucChannelNum; // Number of channel; 7614 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7615 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7616 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7617 UCHAR ucReserved[2]; 7618}ATOM_VRAM_MODULE_V1; 7619 7620 7621typedef struct _ATOM_VRAM_MODULE_V2 7622{ 7623 ULONG ulReserved; 7624 ULONG ulFlags; // To enable/disable functionalities based on memory type 7625 ULONG ulEngineClock; // Override of default engine clock for particular memory type 7626 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 7627 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7628 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7629 USHORT usEMRSValue; 7630 USHORT usMRSValue; 7631 USHORT usReserved; 7632 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7633 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7634 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7635 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7636 UCHAR ucRow; // Number of Row,in power of 2; 7637 UCHAR ucColumn; // Number of Column,in power of 2; 7638 UCHAR ucBank; // Nunber of Bank; 7639 UCHAR ucRank; // Number of Rank, in power of 2 7640 UCHAR ucChannelNum; // Number of channel; 7641 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7642 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7643 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7644 UCHAR ucRefreshRateFactor; 7645 UCHAR ucReserved[3]; 7646}ATOM_VRAM_MODULE_V2; 7647 7648 7649typedef struct _ATOM_MEMORY_TIMING_FORMAT 7650{ 7651 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7652 union{ 7653 USHORT usMRS; // mode register 7654 USHORT usDDR3_MR0; 7655 }; 7656 union{ 7657 USHORT usEMRS; // extended mode register 7658 USHORT usDDR3_MR1; 7659 }; 7660 UCHAR ucCL; // CAS latency 7661 UCHAR ucWL; // WRITE Latency 7662 UCHAR uctRAS; // tRAS 7663 UCHAR uctRC; // tRC 7664 UCHAR uctRFC; // tRFC 7665 UCHAR uctRCDR; // tRCDR 7666 UCHAR uctRCDW; // tRCDW 7667 UCHAR uctRP; // tRP 7668 UCHAR uctRRD; // tRRD 7669 UCHAR uctWR; // tWR 7670 UCHAR uctWTR; // tWTR 7671 UCHAR uctPDIX; // tPDIX 7672 UCHAR uctFAW; // tFAW 7673 UCHAR uctAOND; // tAOND 7674 union 7675 { 7676 struct { 7677 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7678 UCHAR ucReserved; 7679 }; 7680 USHORT usDDR3_MR2; 7681 }; 7682}ATOM_MEMORY_TIMING_FORMAT; 7683 7684 7685typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 7686{ 7687 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7688 USHORT usMRS; // mode register 7689 USHORT usEMRS; // extended mode register 7690 UCHAR ucCL; // CAS latency 7691 UCHAR ucWL; // WRITE Latency 7692 UCHAR uctRAS; // tRAS 7693 UCHAR uctRC; // tRC 7694 UCHAR uctRFC; // tRFC 7695 UCHAR uctRCDR; // tRCDR 7696 UCHAR uctRCDW; // tRCDW 7697 UCHAR uctRP; // tRP 7698 UCHAR uctRRD; // tRRD 7699 UCHAR uctWR; // tWR 7700 UCHAR uctWTR; // tWTR 7701 UCHAR uctPDIX; // tPDIX 7702 UCHAR uctFAW; // tFAW 7703 UCHAR uctAOND; // tAOND 7704 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7705////////////////////////////////////GDDR parameters/////////////////////////////////// 7706 UCHAR uctCCDL; // 7707 UCHAR uctCRCRL; // 7708 UCHAR uctCRCWL; // 7709 UCHAR uctCKE; // 7710 UCHAR uctCKRSE; // 7711 UCHAR uctCKRSX; // 7712 UCHAR uctFAW32; // 7713 UCHAR ucMR5lo; // 7714 UCHAR ucMR5hi; // 7715 UCHAR ucTerminator; 7716}ATOM_MEMORY_TIMING_FORMAT_V1; 7717 7718 7719 7720 7721typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 7722{ 7723 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7724 USHORT usMRS; // mode register 7725 USHORT usEMRS; // extended mode register 7726 UCHAR ucCL; // CAS latency 7727 UCHAR ucWL; // WRITE Latency 7728 UCHAR uctRAS; // tRAS 7729 UCHAR uctRC; // tRC 7730 UCHAR uctRFC; // tRFC 7731 UCHAR uctRCDR; // tRCDR 7732 UCHAR uctRCDW; // tRCDW 7733 UCHAR uctRP; // tRP 7734 UCHAR uctRRD; // tRRD 7735 UCHAR uctWR; // tWR 7736 UCHAR uctWTR; // tWTR 7737 UCHAR uctPDIX; // tPDIX 7738 UCHAR uctFAW; // tFAW 7739 UCHAR uctAOND; // tAOND 7740 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7741////////////////////////////////////GDDR parameters/////////////////////////////////// 7742 UCHAR uctCCDL; // 7743 UCHAR uctCRCRL; // 7744 UCHAR uctCRCWL; // 7745 UCHAR uctCKE; // 7746 UCHAR uctCKRSE; // 7747 UCHAR uctCKRSX; // 7748 UCHAR uctFAW32; // 7749 UCHAR ucMR4lo; // 7750 UCHAR ucMR4hi; // 7751 UCHAR ucMR5lo; // 7752 UCHAR ucMR5hi; // 7753 UCHAR ucTerminator; 7754 UCHAR ucReserved; 7755}ATOM_MEMORY_TIMING_FORMAT_V2; 7756 7757 7758typedef struct _ATOM_MEMORY_FORMAT 7759{ 7760 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7761 union{ 7762 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7763 USHORT usDDR3_Reserved; // Not used for DDR3 memory 7764 }; 7765 union{ 7766 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7767 USHORT usDDR3_MR3; // Used for DDR3 memory 7768 }; 7769 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7770 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7771 UCHAR ucRow; // Number of Row,in power of 2; 7772 UCHAR ucColumn; // Number of Column,in power of 2; 7773 UCHAR ucBank; // Nunber of Bank; 7774 UCHAR ucRank; // Number of Rank, in power of 2 7775 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7776 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7777 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7778 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7779 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7780 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7781 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7782}ATOM_MEMORY_FORMAT; 7783 7784 7785typedef struct _ATOM_VRAM_MODULE_V3 7786{ 7787 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7788 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7789 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7790 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7791 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7792 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7793 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7794 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7795 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7796 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7797 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7798}ATOM_VRAM_MODULE_V3; 7799 7800 7801//ATOM_VRAM_MODULE_V3.ucNPL_RT 7802#define NPL_RT_MASK 0x0f 7803#define BATTERY_ODT_MASK 0xc0 7804 7805#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7806 7807typedef struct _ATOM_VRAM_MODULE_V4 7808{ 7809 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7810 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7811 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7812 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7813 USHORT usReserved; 7814 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7815 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7816 UCHAR ucChannelNum; // Number of channels present in this module config 7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7818 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7819 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7820 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7821 UCHAR ucVREFI; // board dependent parameter 7822 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7823 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7824 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7825 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7826 UCHAR ucReserved[3]; 7827 7828//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7829 union{ 7830 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7831 USHORT usDDR3_Reserved; 7832 }; 7833 union{ 7834 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7835 USHORT usDDR3_MR3; // Used for DDR3 memory 7836 }; 7837 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7838 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7839 UCHAR ucReserved2[2]; 7840 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7841}ATOM_VRAM_MODULE_V4; 7842 7843#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7844#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7845#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7846#define VRAM_MODULE_V4_MISC_BL8 0x4 7847#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7848 7849typedef struct _ATOM_VRAM_MODULE_V5 7850{ 7851 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7852 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7853 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7854 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7855 USHORT usReserved; 7856 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7857 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7858 UCHAR ucChannelNum; // Number of channels present in this module config 7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7860 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7861 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7862 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7863 UCHAR ucVREFI; // board dependent parameter 7864 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7865 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7866 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7867 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7868 UCHAR ucReserved[3]; 7869 7870//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7871 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7872 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7873 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7874 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7875 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7877 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7878}ATOM_VRAM_MODULE_V5; 7879 7880 7881typedef struct _ATOM_VRAM_MODULE_V6 7882{ 7883 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7884 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7885 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7886 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7887 USHORT usReserved; 7888 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7889 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7890 UCHAR ucChannelNum; // Number of channels present in this module config 7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7892 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7893 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7894 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7895 UCHAR ucVREFI; // board dependent parameter 7896 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7897 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7898 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7899 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7900 UCHAR ucReserved[3]; 7901 7902//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7903 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7904 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7905 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7906 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7907 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7909 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7910}ATOM_VRAM_MODULE_V6; 7911 7912typedef struct _ATOM_VRAM_MODULE_V7 7913{ 7914// Design Specific Values 7915 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7916 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7917 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7918 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7919 UCHAR ucExtMemoryID; // Current memory module ID 7920 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7921 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7922 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7923 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7924 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7925 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7926 UCHAR ucVREFI; // Not used. 7927 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7928 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7929 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7930 USHORT usSEQSettingOffset; 7931 UCHAR ucReserved; 7932// Memory Module specific values 7933 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7934 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7935 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7936 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7937 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7939 char strMemPNString[20]; // part number end with '0'. 7940}ATOM_VRAM_MODULE_V7; 7941 7942 7943typedef struct _ATOM_VRAM_MODULE_V8 7944{ 7945// Design Specific Values 7946 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7947 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7948 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7949 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7950 UCHAR ucExtMemoryID; // Current memory module ID 7951 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7952 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7953 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7954 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7955 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7956 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7957 UCHAR ucVREFI; // Not used. 7958 USHORT usReserved; // Not used 7959 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7960 UCHAR ucMcTunningSetId; // MC phy registers set per. 7961 UCHAR ucRowNum; 7962// Memory Module specific values 7963 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7964 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7965 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7966 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7967 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7969 7970 ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7971 ULONG ulBankMapCfg; 7972 ULONG ulReserved; 7973 char strMemPNString[20]; // part number end with '0'. 7974}ATOM_VRAM_MODULE_V8; 7975 7976 7977typedef struct _ATOM_VRAM_INFO_V2 7978{ 7979 ATOM_COMMON_TABLE_HEADER sHeader; 7980 UCHAR ucNumOfVRAMModule; 7981 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7982}ATOM_VRAM_INFO_V2; 7983 7984typedef struct _ATOM_VRAM_INFO_V3 7985{ 7986 ATOM_COMMON_TABLE_HEADER sHeader; 7987 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7988 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7989 USHORT usRerseved; 7990 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7991 UCHAR ucNumOfVRAMModule; 7992 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7993 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7994 7995}ATOM_VRAM_INFO_V3; 7996 7997#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 7998 7999typedef struct _ATOM_VRAM_INFO_V4 8000{ 8001 ATOM_COMMON_TABLE_HEADER sHeader; 8002 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8003 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8004 USHORT usRerseved; 8005 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 8006 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 8007 UCHAR ucReservde[4]; 8008 UCHAR ucNumOfVRAMModule; 8009 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8010 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 8011}ATOM_VRAM_INFO_V4; 8012 8013typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 8014{ 8015 ATOM_COMMON_TABLE_HEADER sHeader; 8016 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8017 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8018 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8019 USHORT usReserved[3]; 8020 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8021 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8022 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8023 UCHAR ucReserved; 8024 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8025}ATOM_VRAM_INFO_HEADER_V2_1; 8026 8027typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 8028{ 8029 ATOM_COMMON_TABLE_HEADER sHeader; 8030 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8031 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8032 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8033 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 8034 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 8035 USHORT usReserved1; 8036 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8037 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8038 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8039 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 8040 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8041}ATOM_VRAM_INFO_HEADER_V2_2; 8042 8043 8044typedef struct _ATOM_DRAM_DATA_REMAP 8045{ 8046 UCHAR ucByteRemapCh0; 8047 UCHAR ucByteRemapCh1; 8048 ULONG ulByte0BitRemapCh0; 8049 ULONG ulByte1BitRemapCh0; 8050 ULONG ulByte2BitRemapCh0; 8051 ULONG ulByte3BitRemapCh0; 8052 ULONG ulByte0BitRemapCh1; 8053 ULONG ulByte1BitRemapCh1; 8054 ULONG ulByte2BitRemapCh1; 8055 ULONG ulByte3BitRemapCh1; 8056}ATOM_DRAM_DATA_REMAP; 8057 8058typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 8059{ 8060 ATOM_COMMON_TABLE_HEADER sHeader; 8061 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 8062}ATOM_VRAM_GPIO_DETECTION_INFO; 8063 8064 8065typedef struct _ATOM_MEMORY_TRAINING_INFO 8066{ 8067 ATOM_COMMON_TABLE_HEADER sHeader; 8068 UCHAR ucTrainingLoop; 8069 UCHAR ucReserved[3]; 8070 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 8071}ATOM_MEMORY_TRAINING_INFO; 8072 8073 8074typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1 8075{ 8076 ATOM_COMMON_TABLE_HEADER sHeader; 8077 ULONG ulMCUcodeVersion; 8078 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array 8079 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array 8080 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array 8081 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array. 8082}ATOM_MEMORY_TRAINING_INFO_V3_1; 8083 8084 8085typedef struct SW_I2C_CNTL_DATA_PARAMETERS 8086{ 8087 UCHAR ucControl; 8088 UCHAR ucData; 8089 UCHAR ucSatus; 8090 UCHAR ucTemp; 8091} SW_I2C_CNTL_DATA_PARAMETERS; 8092 8093#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 8094 8095typedef struct _SW_I2C_IO_DATA_PARAMETERS 8096{ 8097 USHORT GPIO_Info; 8098 UCHAR ucAct; 8099 UCHAR ucData; 8100 } SW_I2C_IO_DATA_PARAMETERS; 8101 8102#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 8103 8104/****************************SW I2C CNTL DEFINITIONS**********************/ 8105#define SW_I2C_IO_RESET 0 8106#define SW_I2C_IO_GET 1 8107#define SW_I2C_IO_DRIVE 2 8108#define SW_I2C_IO_SET 3 8109#define SW_I2C_IO_START 4 8110 8111#define SW_I2C_IO_CLOCK 0 8112#define SW_I2C_IO_DATA 0x80 8113 8114#define SW_I2C_IO_ZERO 0 8115#define SW_I2C_IO_ONE 0x100 8116 8117#define SW_I2C_CNTL_READ 0 8118#define SW_I2C_CNTL_WRITE 1 8119#define SW_I2C_CNTL_START 2 8120#define SW_I2C_CNTL_STOP 3 8121#define SW_I2C_CNTL_OPEN 4 8122#define SW_I2C_CNTL_CLOSE 5 8123#define SW_I2C_CNTL_WRITE1BIT 6 8124 8125//==============================VESA definition Portion=============================== 8126#define VESA_OEM_PRODUCT_REV '01.00' 8127#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 8128#define VESA_MODE_WIN_ATTRIBUTE 7 8129#define VESA_WIN_SIZE 64 8130 8131typedef struct _PTR_32_BIT_STRUCTURE 8132{ 8133 USHORT Offset16; 8134 USHORT Segment16; 8135} PTR_32_BIT_STRUCTURE; 8136 8137typedef union _PTR_32_BIT_UNION 8138{ 8139 PTR_32_BIT_STRUCTURE SegmentOffset; 8140 ULONG Ptr32_Bit; 8141} PTR_32_BIT_UNION; 8142 8143typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 8144{ 8145 UCHAR VbeSignature[4]; 8146 USHORT VbeVersion; 8147 PTR_32_BIT_UNION OemStringPtr; 8148 UCHAR Capabilities[4]; 8149 PTR_32_BIT_UNION VideoModePtr; 8150 USHORT TotalMemory; 8151} VBE_1_2_INFO_BLOCK_UPDATABLE; 8152 8153 8154typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 8155{ 8156 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 8157 USHORT OemSoftRev; 8158 PTR_32_BIT_UNION OemVendorNamePtr; 8159 PTR_32_BIT_UNION OemProductNamePtr; 8160 PTR_32_BIT_UNION OemProductRevPtr; 8161} VBE_2_0_INFO_BLOCK_UPDATABLE; 8162 8163typedef union _VBE_VERSION_UNION 8164{ 8165 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 8166 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 8167} VBE_VERSION_UNION; 8168 8169typedef struct _VBE_INFO_BLOCK 8170{ 8171 VBE_VERSION_UNION UpdatableVBE_Info; 8172 UCHAR Reserved[222]; 8173 UCHAR OemData[256]; 8174} VBE_INFO_BLOCK; 8175 8176typedef struct _VBE_FP_INFO 8177{ 8178 USHORT HSize; 8179 USHORT VSize; 8180 USHORT FPType; 8181 UCHAR RedBPP; 8182 UCHAR GreenBPP; 8183 UCHAR BlueBPP; 8184 UCHAR ReservedBPP; 8185 ULONG RsvdOffScrnMemSize; 8186 ULONG RsvdOffScrnMEmPtr; 8187 UCHAR Reserved[14]; 8188} VBE_FP_INFO; 8189 8190typedef struct _VESA_MODE_INFO_BLOCK 8191{ 8192// Mandatory information for all VBE revisions 8193 USHORT ModeAttributes; // dw ? ; mode attributes 8194 UCHAR WinAAttributes; // db ? ; window A attributes 8195 UCHAR WinBAttributes; // db ? ; window B attributes 8196 USHORT WinGranularity; // dw ? ; window granularity 8197 USHORT WinSize; // dw ? ; window size 8198 USHORT WinASegment; // dw ? ; window A start segment 8199 USHORT WinBSegment; // dw ? ; window B start segment 8200 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 8201 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 8202 8203//; Mandatory information for VBE 1.2 and above 8204 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 8205 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 8206 UCHAR XCharSize; // db ? ; character cell width in pixels 8207 UCHAR YCharSize; // db ? ; character cell height in pixels 8208 UCHAR NumberOfPlanes; // db ? ; number of memory planes 8209 UCHAR BitsPerPixel; // db ? ; bits per pixel 8210 UCHAR NumberOfBanks; // db ? ; number of banks 8211 UCHAR MemoryModel; // db ? ; memory model type 8212 UCHAR BankSize; // db ? ; bank size in KB 8213 UCHAR NumberOfImagePages;// db ? ; number of images 8214 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 8215 8216//; Direct Color fields(required for direct/6 and YUV/7 memory models) 8217 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 8218 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 8219 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 8220 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 8221 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 8222 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 8223 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 8224 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 8225 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 8226 8227//; Mandatory information for VBE 2.0 and above 8228 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 8231 8232//; Mandatory information for VBE 3.0 and above 8233 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 8234 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 8235 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 8236 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 8237 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 8238 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 8239 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 8240 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 8241 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 8242 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 8243 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 8244 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 8245 UCHAR Reserved; // db 190 dup (0) 8246} VESA_MODE_INFO_BLOCK; 8247 8248// BIOS function CALLS 8249#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 8250#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 8251#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 8252#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 8253#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 8254#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 8255#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 8256#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 8257#define ATOM_BIOS_FUNCTION_STV_STD 0x16 8258#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 8259#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 8260 8261#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 8262#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 8263#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 8264#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 8265#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 8266#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 8267#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 8268 8269#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 8270#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 8271#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 8272#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 8273#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 8274#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 8275#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 8276#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 8277#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 8278#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 8279 8280 8281#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 8282#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 8283#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 8284#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 8285#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 8286#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 8287#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 8288#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 8289 8290#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 8291#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 8292#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 8293 8294// structure used for VBIOS only 8295 8296//DispOutInfoTable 8297typedef struct _ASIC_TRANSMITTER_INFO 8298{ 8299 USHORT usTransmitterObjId; 8300 USHORT usSupportDevice; 8301 UCHAR ucTransmitterCmdTblId; 8302 UCHAR ucConfig; 8303 UCHAR ucEncoderID; //available 1st encoder ( default ) 8304 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 8305 UCHAR uc2ndEncoderID; 8306 UCHAR ucReserved; 8307}ASIC_TRANSMITTER_INFO; 8308 8309#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 8310#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 8311#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 8312#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 8313#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 8314#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 8315#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 8316#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 8317#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 8318 8319typedef struct _ASIC_ENCODER_INFO 8320{ 8321 UCHAR ucEncoderID; 8322 UCHAR ucEncoderConfig; 8323 USHORT usEncoderCmdTblId; 8324}ASIC_ENCODER_INFO; 8325 8326typedef struct _ATOM_DISP_OUT_INFO 8327{ 8328 ATOM_COMMON_TABLE_HEADER sHeader; 8329 USHORT ptrTransmitterInfo; 8330 USHORT ptrEncoderInfo; 8331 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8332 ASIC_ENCODER_INFO asEncoderInfo[1]; 8333}ATOM_DISP_OUT_INFO; 8334 8335 8336typedef struct _ATOM_DISP_OUT_INFO_V2 8337{ 8338 ATOM_COMMON_TABLE_HEADER sHeader; 8339 USHORT ptrTransmitterInfo; 8340 USHORT ptrEncoderInfo; 8341 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8342 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8343 ASIC_ENCODER_INFO asEncoderInfo[1]; 8344}ATOM_DISP_OUT_INFO_V2; 8345 8346 8347typedef struct _ATOM_DISP_CLOCK_ID { 8348 UCHAR ucPpllId; 8349 UCHAR ucPpllAttribute; 8350}ATOM_DISP_CLOCK_ID; 8351 8352// ucPpllAttribute 8353#define CLOCK_SOURCE_SHAREABLE 0x01 8354#define CLOCK_SOURCE_DP_MODE 0x02 8355#define CLOCK_SOURCE_NONE_DP_MODE 0x04 8356 8357//DispOutInfoTable 8358typedef struct _ASIC_TRANSMITTER_INFO_V2 8359{ 8360 USHORT usTransmitterObjId; 8361 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 8362 UCHAR ucTransmitterCmdTblId; 8363 UCHAR ucConfig; 8364 UCHAR ucEncoderID; // available 1st encoder ( default ) 8365 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 8366 UCHAR uc2ndEncoderID; 8367 UCHAR ucReserved; 8368}ASIC_TRANSMITTER_INFO_V2; 8369 8370typedef struct _ATOM_DISP_OUT_INFO_V3 8371{ 8372 ATOM_COMMON_TABLE_HEADER sHeader; 8373 USHORT ptrTransmitterInfo; 8374 USHORT ptrEncoderInfo; 8375 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8376 USHORT usReserved; 8377 UCHAR ucDCERevision; 8378 UCHAR ucMaxDispEngineNum; 8379 UCHAR ucMaxActiveDispEngineNum; 8380 UCHAR ucMaxPPLLNum; 8381 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 8382 UCHAR ucDispCaps; 8383 UCHAR ucReserved[2]; 8384 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 8385}ATOM_DISP_OUT_INFO_V3; 8386 8387//ucDispCaps 8388#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 8389#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 8390 8391typedef enum CORE_REF_CLK_SOURCE{ 8392 CLOCK_SRC_XTALIN=0, 8393 CLOCK_SRC_XO_IN=1, 8394 CLOCK_SRC_XO_IN2=2, 8395}CORE_REF_CLK_SOURCE; 8396 8397// DispDevicePriorityInfo 8398typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 8399{ 8400 ATOM_COMMON_TABLE_HEADER sHeader; 8401 USHORT asDevicePriority[16]; 8402}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 8403 8404//ProcessAuxChannelTransactionTable 8405typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8406{ 8407 USHORT lpAuxRequest; 8408 USHORT lpDataOut; 8409 UCHAR ucChannelID; 8410 union 8411 { 8412 UCHAR ucReplyStatus; 8413 UCHAR ucDelay; 8414 }; 8415 UCHAR ucDataOutLen; 8416 UCHAR ucReserved; 8417}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 8418 8419//ProcessAuxChannelTransactionTable 8420typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 8421{ 8422 USHORT lpAuxRequest; 8423 USHORT lpDataOut; 8424 UCHAR ucChannelID; 8425 union 8426 { 8427 UCHAR ucReplyStatus; 8428 UCHAR ucDelay; 8429 }; 8430 UCHAR ucDataOutLen; 8431 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 8432}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 8433 8434#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8435 8436//GetSinkType 8437 8438typedef struct _DP_ENCODER_SERVICE_PARAMETERS 8439{ 8440 USHORT ucLinkClock; 8441 union 8442 { 8443 UCHAR ucConfig; // for DP training command 8444 UCHAR ucI2cId; // use for GET_SINK_TYPE command 8445 }; 8446 UCHAR ucAction; 8447 UCHAR ucStatus; 8448 UCHAR ucLaneNum; 8449 UCHAR ucReserved[2]; 8450}DP_ENCODER_SERVICE_PARAMETERS; 8451 8452// ucAction 8453#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 8454 8455#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 8456 8457 8458typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 8459{ 8460 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8461 UCHAR ucAuxId; 8462 UCHAR ucAction; 8463 UCHAR ucSinkType; // Iput and Output parameters. 8464 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8465 UCHAR ucReserved[2]; 8466}DP_ENCODER_SERVICE_PARAMETERS_V2; 8467 8468typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 8469{ 8470 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 8471 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 8472}DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 8473 8474// ucAction 8475#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 8476#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 8477 8478 8479// DP_TRAINING_TABLE 8480#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 8481#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 8482#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 8483#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 8484#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 8485#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 8486#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 8487#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 8488#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 8489#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 8490#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 8491#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 8492#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 8493 8494 8495typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8496{ 8497 UCHAR ucI2CSpeed; 8498 union 8499 { 8500 UCHAR ucRegIndex; 8501 UCHAR ucStatus; 8502 }; 8503 USHORT lpI2CDataOut; 8504 UCHAR ucFlag; 8505 UCHAR ucTransBytes; 8506 UCHAR ucSlaveAddr; 8507 UCHAR ucLineNumber; 8508}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 8509 8510#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8511 8512//ucFlag 8513#define HW_I2C_WRITE 1 8514#define HW_I2C_READ 0 8515#define I2C_2BYTE_ADDR 0x02 8516 8517/****************************************************************************/ 8518// Structures used by HW_Misc_OperationTable 8519/****************************************************************************/ 8520typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 8521{ 8522 UCHAR ucCmd; // Input: To tell which action to take 8523 UCHAR ucReserved[3]; 8524 ULONG ulReserved; 8525}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 8526 8527typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 8528{ 8529 UCHAR ucReturnCode; // Output: Return value base on action was taken 8530 UCHAR ucReserved[3]; 8531 ULONG ulReserved; 8532}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 8533 8534// Actions code 8535#define ATOM_GET_SDI_SUPPORT 0xF0 8536 8537// Return code 8538#define ATOM_UNKNOWN_CMD 0 8539#define ATOM_FEATURE_NOT_SUPPORTED 1 8540#define ATOM_FEATURE_SUPPORTED 2 8541 8542typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 8543{ 8544 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 8545 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 8546}ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 8547 8548/****************************************************************************/ 8549 8550typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 8551{ 8552 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 8553 UCHAR ucReserved[3]; 8554}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 8555 8556#define HWBLKINST_INSTANCE_MASK 0x07 8557#define HWBLKINST_HWBLK_MASK 0xF0 8558#define HWBLKINST_HWBLK_SHIFT 0x04 8559 8560//ucHWBlock 8561#define SELECT_DISP_ENGINE 0 8562#define SELECT_DISP_PLL 1 8563#define SELECT_DCIO_UNIPHY_LINK0 2 8564#define SELECT_DCIO_UNIPHY_LINK1 3 8565#define SELECT_DCIO_IMPCAL 4 8566#define SELECT_DCIO_DIG 6 8567#define SELECT_CRTC_PIXEL_RATE 7 8568#define SELECT_VGA_BLK 8 8569 8570// DIGTransmitterInfoTable structure used to program UNIPHY settings 8571typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 8572 ATOM_COMMON_TABLE_HEADER sHeader; 8573 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8574 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8575 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8576 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8577 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8578}DIG_TRANSMITTER_INFO_HEADER_V3_1; 8579 8580typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 8581 ATOM_COMMON_TABLE_HEADER sHeader; 8582 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8583 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8584 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8585 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8586 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8587 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8588 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8589}DIG_TRANSMITTER_INFO_HEADER_V3_2; 8590 8591 8592typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 8593 ATOM_COMMON_TABLE_HEADER sHeader; 8594 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8595 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8596 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8597 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8598 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8599 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8600 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8601 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 8602 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8603 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8604 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 8605 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8606 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 8607}DIG_TRANSMITTER_INFO_HEADER_V3_3; 8608 8609 8610typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 8611 USHORT usRegisterIndex; 8612 UCHAR ucStartBit; 8613 UCHAR ucEndBit; 8614}CLOCK_CONDITION_REGESTER_INFO; 8615 8616typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 8617 USHORT usMaxClockFreq; 8618 UCHAR ucEncodeMode; 8619 UCHAR ucPhySel; 8620 ULONG ulAnalogSetting[1]; 8621}CLOCK_CONDITION_SETTING_ENTRY; 8622 8623typedef struct _CLOCK_CONDITION_SETTING_INFO{ 8624 USHORT usEntrySize; 8625 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 8626}CLOCK_CONDITION_SETTING_INFO; 8627 8628typedef struct _PHY_CONDITION_REG_VAL{ 8629 ULONG ulCondition; 8630 ULONG ulRegVal; 8631}PHY_CONDITION_REG_VAL; 8632 8633typedef struct _PHY_CONDITION_REG_VAL_V2{ 8634 ULONG ulCondition; 8635 UCHAR ucCondition2; 8636 ULONG ulRegVal; 8637}PHY_CONDITION_REG_VAL_V2; 8638 8639typedef struct _PHY_CONDITION_REG_INFO{ 8640 USHORT usRegIndex; 8641 USHORT usSize; 8642 PHY_CONDITION_REG_VAL asRegVal[1]; 8643}PHY_CONDITION_REG_INFO; 8644 8645typedef struct _PHY_CONDITION_REG_INFO_V2{ 8646 USHORT usRegIndex; 8647 USHORT usSize; 8648 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 8649}PHY_CONDITION_REG_INFO_V2; 8650 8651typedef struct _PHY_ANALOG_SETTING_INFO{ 8652 UCHAR ucEncodeMode; 8653 UCHAR ucPhySel; 8654 USHORT usSize; 8655 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 8656}PHY_ANALOG_SETTING_INFO; 8657 8658typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 8659 UCHAR ucEncodeMode; 8660 UCHAR ucPhySel; 8661 USHORT usSize; 8662 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 8663}PHY_ANALOG_SETTING_INFO_V2; 8664 8665 8666typedef struct _GFX_HAVESTING_PARAMETERS { 8667 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 8668 UCHAR ucReserved; //reserved 8669 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 8670 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 8671} GFX_HAVESTING_PARAMETERS; 8672 8673//ucGfxBlkId 8674#define GFX_HARVESTING_CU_ID 0 8675#define GFX_HARVESTING_RB_ID 1 8676#define GFX_HARVESTING_PRIM_ID 2 8677 8678 8679typedef struct _VBIOS_ROM_HEADER{ 8680 UCHAR PciRomSignature[2]; 8681 UCHAR ucPciRomSizeIn512bytes; 8682 UCHAR ucJumpCoreMainInitBIOS; 8683 USHORT usLabelCoreMainInitBIOS; 8684 UCHAR PciReservedSpace[18]; 8685 USHORT usPciDataStructureOffset; 8686 UCHAR Rsvd1d_1a[4]; 8687 char strIbm[3]; 8688 UCHAR CheckSum[14]; 8689 UCHAR ucBiosMsgNumber; 8690 char str761295520[16]; 8691 USHORT usLabelCoreVPOSTNoMode; 8692 USHORT usSpecialPostOffset; 8693 UCHAR ucSpeicalPostImageSizeIn512Bytes; 8694 UCHAR Rsved47_45[3]; 8695 USHORT usROM_HeaderInformationTableOffset; 8696 UCHAR Rsved4f_4a[6]; 8697 char strBuildTimeStamp[20]; 8698 UCHAR ucJumpCoreXFuncFarHandler; 8699 USHORT usCoreXFuncFarHandlerOffset; 8700 UCHAR ucRsved67; 8701 UCHAR ucJumpCoreVFuncFarHandler; 8702 USHORT usCoreVFuncFarHandlerOffset; 8703 UCHAR Rsved6d_6b[3]; 8704 USHORT usATOM_BIOS_MESSAGE_Offset; 8705}VBIOS_ROM_HEADER; 8706 8707/****************************************************************************/ 8708//Portion VI: Definitinos for vbios MC scratch registers that driver used 8709/****************************************************************************/ 8710 8711#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 8712#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 8713#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 8714#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 8715#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 8716#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 8717#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 8718#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 8719 8720#define ATOM_MEM_TYPE_DDR_STRING "DDR" 8721#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 8722#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 8723#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 8724#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 8725#define ATOM_MEM_TYPE_HBM_STRING "HBM" 8726#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 8727 8728/****************************************************************************/ 8729//Portion VII: Definitinos being oboselete 8730/****************************************************************************/ 8731 8732//========================================================================================== 8733//Remove the definitions below when driver is ready! 8734typedef struct _ATOM_DAC_INFO 8735{ 8736 ATOM_COMMON_TABLE_HEADER sHeader; 8737 USHORT usMaxFrequency; // in 10kHz unit 8738 USHORT usReserved; 8739}ATOM_DAC_INFO; 8740 8741 8742typedef struct _COMPASSIONATE_DATA 8743{ 8744 ATOM_COMMON_TABLE_HEADER sHeader; 8745 8746 //============================== DAC1 portion 8747 UCHAR ucDAC1_BG_Adjustment; 8748 UCHAR ucDAC1_DAC_Adjustment; 8749 USHORT usDAC1_FORCE_Data; 8750 //============================== DAC2 portion 8751 UCHAR ucDAC2_CRT2_BG_Adjustment; 8752 UCHAR ucDAC2_CRT2_DAC_Adjustment; 8753 USHORT usDAC2_CRT2_FORCE_Data; 8754 USHORT usDAC2_CRT2_MUX_RegisterIndex; 8755 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8756 UCHAR ucDAC2_NTSC_BG_Adjustment; 8757 UCHAR ucDAC2_NTSC_DAC_Adjustment; 8758 USHORT usDAC2_TV1_FORCE_Data; 8759 USHORT usDAC2_TV1_MUX_RegisterIndex; 8760 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8761 UCHAR ucDAC2_CV_BG_Adjustment; 8762 UCHAR ucDAC2_CV_DAC_Adjustment; 8763 USHORT usDAC2_CV_FORCE_Data; 8764 USHORT usDAC2_CV_MUX_RegisterIndex; 8765 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8766 UCHAR ucDAC2_PAL_BG_Adjustment; 8767 UCHAR ucDAC2_PAL_DAC_Adjustment; 8768 USHORT usDAC2_TV2_FORCE_Data; 8769}COMPASSIONATE_DATA; 8770 8771/****************************Supported Device Info Table Definitions**********************/ 8772// ucConnectInfo: 8773// [7:4] - connector type 8774// = 1 - VGA connector 8775// = 2 - DVI-I 8776// = 3 - DVI-D 8777// = 4 - DVI-A 8778// = 5 - SVIDEO 8779// = 6 - COMPOSITE 8780// = 7 - LVDS 8781// = 8 - DIGITAL LINK 8782// = 9 - SCART 8783// = 0xA - HDMI_type A 8784// = 0xB - HDMI_type B 8785// = 0xE - Special case1 (DVI+DIN) 8786// Others=TBD 8787// [3:0] - DAC Associated 8788// = 0 - no DAC 8789// = 1 - DACA 8790// = 2 - DACB 8791// = 3 - External DAC 8792// Others=TBD 8793// 8794 8795typedef struct _ATOM_CONNECTOR_INFO 8796{ 8797#if ATOM_BIG_ENDIAN 8798 UCHAR bfConnectorType:4; 8799 UCHAR bfAssociatedDAC:4; 8800#else 8801 UCHAR bfAssociatedDAC:4; 8802 UCHAR bfConnectorType:4; 8803#endif 8804}ATOM_CONNECTOR_INFO; 8805 8806typedef union _ATOM_CONNECTOR_INFO_ACCESS 8807{ 8808 ATOM_CONNECTOR_INFO sbfAccess; 8809 UCHAR ucAccess; 8810}ATOM_CONNECTOR_INFO_ACCESS; 8811 8812typedef struct _ATOM_CONNECTOR_INFO_I2C 8813{ 8814 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8815 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8816}ATOM_CONNECTOR_INFO_I2C; 8817 8818 8819typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8820{ 8821 ATOM_COMMON_TABLE_HEADER sHeader; 8822 USHORT usDeviceSupport; 8823 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8824}ATOM_SUPPORTED_DEVICES_INFO; 8825 8826#define NO_INT_SRC_MAPPED 0xFF 8827 8828typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8829{ 8830 UCHAR ucIntSrcBitmap; 8831}ATOM_CONNECTOR_INC_SRC_BITMAP; 8832 8833typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8834{ 8835 ATOM_COMMON_TABLE_HEADER sHeader; 8836 USHORT usDeviceSupport; 8837 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8838 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8839}ATOM_SUPPORTED_DEVICES_INFO_2; 8840 8841typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8842{ 8843 ATOM_COMMON_TABLE_HEADER sHeader; 8844 USHORT usDeviceSupport; 8845 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8846 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8847}ATOM_SUPPORTED_DEVICES_INFO_2d1; 8848 8849#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8850 8851 8852 8853typedef struct _ATOM_MISC_CONTROL_INFO 8854{ 8855 USHORT usFrequency; 8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8857 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8858 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8859 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8860}ATOM_MISC_CONTROL_INFO; 8861 8862 8863#define ATOM_MAX_MISC_INFO 4 8864 8865typedef struct _ATOM_TMDS_INFO 8866{ 8867 ATOM_COMMON_TABLE_HEADER sHeader; 8868 USHORT usMaxFrequency; // in 10Khz 8869 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8870}ATOM_TMDS_INFO; 8871 8872 8873typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8874{ 8875 UCHAR ucTVStandard; //Same as TV standards defined above, 8876 UCHAR ucPadding[1]; 8877}ATOM_ENCODER_ANALOG_ATTRIBUTE; 8878 8879typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8880{ 8881 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8882 UCHAR ucPadding[1]; 8883}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8884 8885typedef union _ATOM_ENCODER_ATTRIBUTE 8886{ 8887 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8888 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8889}ATOM_ENCODER_ATTRIBUTE; 8890 8891 8892typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8893{ 8894 USHORT usPixelClock; 8895 USHORT usEncoderID; 8896 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8897 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8898 ATOM_ENCODER_ATTRIBUTE usDevAttr; 8899}DVO_ENCODER_CONTROL_PARAMETERS; 8900 8901typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8902{ 8903 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8904 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8905}DVO_ENCODER_CONTROL_PS_ALLOCATION; 8906 8907 8908#define ATOM_XTMDS_ASIC_SI164_ID 1 8909#define ATOM_XTMDS_ASIC_SI178_ID 2 8910#define ATOM_XTMDS_ASIC_TFP513_ID 3 8911#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8912#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8913#define ATOM_XTMDS_MVPU_FPGA 0x00000004 8914 8915 8916typedef struct _ATOM_XTMDS_INFO 8917{ 8918 ATOM_COMMON_TABLE_HEADER sHeader; 8919 USHORT usSingleLinkMaxFrequency; 8920 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8921 UCHAR ucXtransimitterID; 8922 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8923 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8924 // due to design. This ID is used to alert driver that the sequence is not "standard"! 8925 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8926 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8927}ATOM_XTMDS_INFO; 8928 8929typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8930{ 8931 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8932 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8933 UCHAR ucPadding[2]; 8934}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8935 8936/****************************Legacy Power Play Table Definitions **********************/ 8937 8938//Definitions for ulPowerPlayMiscInfo 8939#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8940#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8941#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8942 8943#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8944#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8945 8946#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8947 8948#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8949#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8950#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8951 8952#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8953#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8954#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8955#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8956#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8957#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8958#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8959 8960#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8961#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8962#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8963#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8964#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8965 8966#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8967#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8968 8969#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8970#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8971#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8972#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8973#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8974#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8975 8976#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8977#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8978#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8979 8980#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8981#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8982#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8983#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8984#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8985#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8986#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8987 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8988#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8989#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8990#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8991 8992//ucTableFormatRevision=1 8993//ucTableContentRevision=1 8994typedef struct _ATOM_POWERMODE_INFO 8995{ 8996 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8997 ULONG ulReserved1; // must set to 0 8998 ULONG ulReserved2; // must set to 0 8999 USHORT usEngineClock; 9000 USHORT usMemoryClock; 9001 UCHAR ucVoltageDropIndex; // index to GPIO table 9002 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9003 UCHAR ucMinTemperature; 9004 UCHAR ucMaxTemperature; 9005 UCHAR ucNumPciELanes; // number of PCIE lanes 9006}ATOM_POWERMODE_INFO; 9007 9008//ucTableFormatRevision=2 9009//ucTableContentRevision=1 9010typedef struct _ATOM_POWERMODE_INFO_V2 9011{ 9012 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9013 ULONG ulMiscInfo2; 9014 ULONG ulEngineClock; 9015 ULONG ulMemoryClock; 9016 UCHAR ucVoltageDropIndex; // index to GPIO table 9017 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9018 UCHAR ucMinTemperature; 9019 UCHAR ucMaxTemperature; 9020 UCHAR ucNumPciELanes; // number of PCIE lanes 9021}ATOM_POWERMODE_INFO_V2; 9022 9023//ucTableFormatRevision=2 9024//ucTableContentRevision=2 9025typedef struct _ATOM_POWERMODE_INFO_V3 9026{ 9027 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9028 ULONG ulMiscInfo2; 9029 ULONG ulEngineClock; 9030 ULONG ulMemoryClock; 9031 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 9032 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9033 UCHAR ucMinTemperature; 9034 UCHAR ucMaxTemperature; 9035 UCHAR ucNumPciELanes; // number of PCIE lanes 9036 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 9037}ATOM_POWERMODE_INFO_V3; 9038 9039 9040#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 9041 9042#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 9043#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 9044 9045#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 9046#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 9047#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 9048#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 9049#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 9050#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 9051#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 9052 9053 9054typedef struct _ATOM_POWERPLAY_INFO 9055{ 9056 ATOM_COMMON_TABLE_HEADER sHeader; 9057 UCHAR ucOverdriveThermalController; 9058 UCHAR ucOverdriveI2cLine; 9059 UCHAR ucOverdriveIntBitmap; 9060 UCHAR ucOverdriveControllerAddress; 9061 UCHAR ucSizeOfPowerModeEntry; 9062 UCHAR ucNumOfPowerModeEntries; 9063 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9064}ATOM_POWERPLAY_INFO; 9065 9066typedef struct _ATOM_POWERPLAY_INFO_V2 9067{ 9068 ATOM_COMMON_TABLE_HEADER sHeader; 9069 UCHAR ucOverdriveThermalController; 9070 UCHAR ucOverdriveI2cLine; 9071 UCHAR ucOverdriveIntBitmap; 9072 UCHAR ucOverdriveControllerAddress; 9073 UCHAR ucSizeOfPowerModeEntry; 9074 UCHAR ucNumOfPowerModeEntries; 9075 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9076}ATOM_POWERPLAY_INFO_V2; 9077 9078typedef struct _ATOM_POWERPLAY_INFO_V3 9079{ 9080 ATOM_COMMON_TABLE_HEADER sHeader; 9081 UCHAR ucOverdriveThermalController; 9082 UCHAR ucOverdriveI2cLine; 9083 UCHAR ucOverdriveIntBitmap; 9084 UCHAR ucOverdriveControllerAddress; 9085 UCHAR ucSizeOfPowerModeEntry; 9086 UCHAR ucNumOfPowerModeEntries; 9087 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9088}ATOM_POWERPLAY_INFO_V3; 9089 9090 9091 9092/**************************************************************************/ 9093 9094 9095// Following definitions are for compatiblity issue in different SW components. 9096#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 9097#define Object_Info Object_Header 9098#define AdjustARB_SEQ MC_InitParameter 9099#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 9100#define ASIC_VDDCI_Info ASIC_ProfilingInfo 9101#define ASIC_MVDDQ_Info MemoryTrainingInfo 9102#define SS_Info PPLL_SS_Info 9103#define ASIC_MVDDC_Info ASIC_InternalSS_Info 9104#define DispDevicePriorityInfo SaveRestoreInfo 9105#define DispOutInfo TV_VideoMode 9106 9107 9108#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 9109#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 9110 9111//New device naming, remove them when both DAL/VBIOS is ready 9112#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9113#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 9114 9115#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9116#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 9117 9118#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 9119#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 9120 9121#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 9122#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 9123 9124#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 9125#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 9126 9127#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 9128#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 9129 9130#define ATOM_S0_DFP1I ATOM_S0_DFP1 9131#define ATOM_S0_DFP1X ATOM_S0_DFP2 9132 9133#define ATOM_S0_DFP2I 0x00200000L 9134#define ATOM_S0_DFP2Ib2 0x20 9135 9136#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 9137#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 9138 9139#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 9140#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 9141 9142#define ATOM_S3_DFP2I_ACTIVEb1 0x02 9143 9144#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 9145#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 9146 9147#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 9148 9149#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 9150#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 9151#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 9152 9153 9154#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 9155#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 9156 9157#define ATOM_S5_DOS_REQ_DFP2I 0x0200 9158#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 9159#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 9160 9161#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 9162#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 9163 9164#define TMDS1XEncoderControl DVOEncoderControl 9165#define DFP1XOutputControl DVOOutputControl 9166 9167#define ExternalDFPOutputControl DFP1XOutputControl 9168#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 9169 9170#define DFP1IOutputControl TMDSAOutputControl 9171#define DFP2IOutputControl LVTMAOutputControl 9172 9173#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9174#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9175 9176#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9177#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9178 9179#define ucDac1Standard ucDacStandard 9180#define ucDac2Standard ucDacStandard 9181 9182#define TMDS1EncoderControl TMDSAEncoderControl 9183#define TMDS2EncoderControl LVTMAEncoderControl 9184 9185#define DFP1OutputControl TMDSAOutputControl 9186#define DFP2OutputControl LVTMAOutputControl 9187#define CRT1OutputControl DAC1OutputControl 9188#define CRT2OutputControl DAC2OutputControl 9189 9190//These two lines will be removed for sure in a few days, will follow up with Michael V. 9191#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 9192#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 9193 9194#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 9195#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9196#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9197#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9198#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9199 9200#define ATOM_S6_ACC_REQ_TV2 0x00400000L 9201#define ATOM_DEVICE_TV2_INDEX 0x00000006 9202#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 9203#define ATOM_S0_TV2 0x00100000L 9204#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 9205#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 9206 9207/*********************************************************************************/ 9208 9209#pragma pack() // BIOS data must use byte alignment 9210 9211#pragma pack(1) 9212 9213typedef struct _ATOM_HOLE_INFO 9214{ 9215 USHORT usOffset; // offset of the hole ( from the start of the binary ) 9216 USHORT usLength; // length of the hole ( in bytes ) 9217}ATOM_HOLE_INFO; 9218 9219typedef struct _ATOM_SERVICE_DESCRIPTION 9220{ 9221 UCHAR ucRevision; // Holes set revision 9222 UCHAR ucAlgorithm; // Hash algorithm 9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 9224 UCHAR ucReserved; 9225 USHORT usSigOffset; // Signature offset ( from the start of the binary ) 9226 USHORT usSigLength; // Signature length 9227}ATOM_SERVICE_DESCRIPTION; 9228 9229 9230typedef struct _ATOM_SERVICE_INFO 9231{ 9232 ATOM_COMMON_TABLE_HEADER asHeader; 9233 ATOM_SERVICE_DESCRIPTION asDescr; 9234 UCHAR ucholesNo; // number of holes that follow 9235 ATOM_HOLE_INFO holes[1]; // array of hole descriptions 9236}ATOM_SERVICE_INFO; 9237 9238 9239 9240#pragma pack() // BIOS data must use byte alignment 9241 9242// 9243// AMD ACPI Table 9244// 9245#pragma pack(1) 9246 9247typedef struct { 9248 ULONG Signature; 9249 ULONG TableLength; //Length 9250 UCHAR Revision; 9251 UCHAR Checksum; 9252 UCHAR OemId[6]; 9253 UCHAR OemTableId[8]; //UINT64 OemTableId; 9254 ULONG OemRevision; 9255 ULONG CreatorId; 9256 ULONG CreatorRevision; 9257} AMD_ACPI_DESCRIPTION_HEADER; 9258/* 9259//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 9260typedef struct { 9261 UINT32 Signature; //0x0 9262 UINT32 Length; //0x4 9263 UINT8 Revision; //0x8 9264 UINT8 Checksum; //0x9 9265 UINT8 OemId[6]; //0xA 9266 UINT64 OemTableId; //0x10 9267 UINT32 OemRevision; //0x18 9268 UINT32 CreatorId; //0x1C 9269 UINT32 CreatorRevision; //0x20 9270}EFI_ACPI_DESCRIPTION_HEADER; 9271*/ 9272typedef struct { 9273 AMD_ACPI_DESCRIPTION_HEADER SHeader; 9274 UCHAR TableUUID[16]; //0x24 9275 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 9276 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 9277 ULONG Reserved[4]; //0x3C 9278}UEFI_ACPI_VFCT; 9279 9280typedef struct { 9281 ULONG PCIBus; //0x4C 9282 ULONG PCIDevice; //0x50 9283 ULONG PCIFunction; //0x54 9284 USHORT VendorID; //0x58 9285 USHORT DeviceID; //0x5A 9286 USHORT SSVID; //0x5C 9287 USHORT SSID; //0x5E 9288 ULONG Revision; //0x60 9289 ULONG ImageLength; //0x64 9290}VFCT_IMAGE_HEADER; 9291 9292 9293typedef struct { 9294 VFCT_IMAGE_HEADER VbiosHeader; 9295 UCHAR VbiosContent[]; 9296}GOP_VBIOS_CONTENT; 9297 9298typedef struct { 9299 VFCT_IMAGE_HEADER Lib1Header; 9300 UCHAR Lib1Content[1]; 9301}GOP_LIB1_CONTENT; 9302 9303#pragma pack() 9304 9305 9306#endif /* _ATOMBIOS_H */ 9307 9308#include "pptable.h" 9309 9310