Lines Matching refs:DMUB_SR
36 DMUB_SR(DMCUB_CNTL) \
37 DMUB_SR(DMCUB_CNTL2) \
38 DMUB_SR(DMCUB_SEC_CNTL) \
39 DMUB_SR(DMCUB_INBOX0_SIZE) \
40 DMUB_SR(DMCUB_INBOX0_RPTR) \
41 DMUB_SR(DMCUB_INBOX0_WPTR) \
42 DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
43 DMUB_SR(DMCUB_INBOX1_SIZE) \
44 DMUB_SR(DMCUB_INBOX1_RPTR) \
45 DMUB_SR(DMCUB_INBOX1_WPTR) \
46 DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
47 DMUB_SR(DMCUB_OUTBOX0_SIZE) \
48 DMUB_SR(DMCUB_OUTBOX0_RPTR) \
49 DMUB_SR(DMCUB_OUTBOX0_WPTR) \
50 DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
51 DMUB_SR(DMCUB_OUTBOX1_SIZE) \
52 DMUB_SR(DMCUB_OUTBOX1_RPTR) \
53 DMUB_SR(DMCUB_OUTBOX1_WPTR) \
54 DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
55 DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
56 DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
57 DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
58 DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
59 DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
60 DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
61 DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
62 DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
63 DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
64 DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
65 DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
66 DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
67 DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
68 DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
69 DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
70 DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
71 DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
72 DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
73 DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
74 DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
75 DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
76 DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
77 DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
78 DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
79 DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
80 DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
81 DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
82 DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
83 DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
84 DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
85 DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
86 DMUB_SR(DMCUB_REGION4_OFFSET) \
87 DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
88 DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
89 DMUB_SR(DMCUB_REGION5_OFFSET) \
90 DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
91 DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
92 DMUB_SR(DMCUB_SCRATCH0) \
93 DMUB_SR(DMCUB_SCRATCH1) \
94 DMUB_SR(DMCUB_SCRATCH2) \
95 DMUB_SR(DMCUB_SCRATCH3) \
96 DMUB_SR(DMCUB_SCRATCH4) \
97 DMUB_SR(DMCUB_SCRATCH5) \
98 DMUB_SR(DMCUB_SCRATCH6) \
99 DMUB_SR(DMCUB_SCRATCH7) \
100 DMUB_SR(DMCUB_SCRATCH8) \
101 DMUB_SR(DMCUB_SCRATCH9) \
102 DMUB_SR(DMCUB_SCRATCH10) \
103 DMUB_SR(DMCUB_SCRATCH11) \
104 DMUB_SR(DMCUB_SCRATCH12) \
105 DMUB_SR(DMCUB_SCRATCH13) \
106 DMUB_SR(DMCUB_SCRATCH14) \
107 DMUB_SR(DMCUB_SCRATCH15) \
108 DMUB_SR(DMCUB_GPINT_DATAIN1) \
109 DMUB_SR(DMCUB_GPINT_DATAOUT) \
110 DMUB_SR(CC_DC_PIPE_DIS) \
111 DMUB_SR(MMHUBBUB_SOFT_RESET) \
112 DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
113 DMUB_SR(DCN_VM_FB_OFFSET) \
114 DMUB_SR(DMCUB_TIMER_CURRENT) \
115 DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
116 DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
117 DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
118 DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
119 DMUB_SR(DMCUB_INTERRUPT_ACK)
158 #define DMUB_SR(reg) uint32_t reg;
161 #undef DMUB_SR