Lines Matching defs:vlevel
1840 int vlevel,
1903 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1904 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
1905 v->ModeSupport[vlevel][0])
1908 if (vlevel > context->bw_ctx.dml.soc.num_states)
1909 vlevel = vlevel_split;
1927 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1929 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1943 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1947 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1955 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2014 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
2016 dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
2022 return vlevel;
2036 int pipe_cnt, i, pipe_idx, vlevel;
2055 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2057 if (vlevel > context->bw_ctx.dml.soc.num_states)
2060 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2104 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
2135 *vlevel_out = vlevel;