Lines Matching defs:soc
459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
460 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
461 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
472 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
474 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
477 context->bw_ctx.dml.soc.sr_exit_time_us =
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
495 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
657 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
685 /* Setup soc to always use max dispclk/dppclk to avoid odm-to-lower-voltage */
810 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
821 int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc)
823 return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0);
827 struct _vcs_dpi_soc_bounding_box_st *soc,
833 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp