Lines Matching refs:id
33 #define DPP_REG_LIST_DCN30_COMMON(id)\
34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 SRI(CM_GAMCOR_LUT_DATA, CM, id),\
44 SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\
45 SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\
46 SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\
47 SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\
48 SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\
49 SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\
50 SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\
51 SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\
52 SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\
53 SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\
54 SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\
55 SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\
56 SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\
57 SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\
58 SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\
59 SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\
60 SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\
61 SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\
62 SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\
63 SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\
64 SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\
65 SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\
66 SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\
67 SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\
68 SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\
69 SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\
70 SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\
71 SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\
72 SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\
73 SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\
74 SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\
75 SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\
76 SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\
77 SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\
78 SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\
79 SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\
80 SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\
81 SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\
82 SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\
83 SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\
84 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
85 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
86 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
87 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
88 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
89 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
90 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
91 SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
92 SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
93 SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
94 SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
95 SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
96 SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
97 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
98 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
99 SRI(OTG_H_BLANK, DSCL, id), \
100 SRI(OTG_V_BLANK, DSCL, id), \
101 SRI(SCL_MODE, DSCL, id), \
102 SRI(LB_DATA_FORMAT, DSCL, id), \
103 SRI(LB_MEMORY_CTRL, DSCL, id), \
104 SRI(DSCL_AUTOCAL, DSCL, id), \
105 SRI(DSCL_CONTROL, DSCL, id), \
106 SRI(SCL_TAP_CONTROL, DSCL, id), \
107 SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
108 SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
109 SRI(DSCL_2TAP_CONTROL, DSCL, id), \
110 SRI(MPC_SIZE, DSCL, id), \
111 SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
112 SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
113 SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
114 SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
115 SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
116 SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
117 SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
118 SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
119 SRI(RECOUT_START, DSCL, id), \
120 SRI(RECOUT_SIZE, DSCL, id), \
121 SRI(PRE_DEALPHA, CNVC_CFG, id), \
122 SRI(PRE_REALPHA, CNVC_CFG, id), \
123 SRI(PRE_CSC_MODE, CNVC_CFG, id), \
124 SRI(PRE_CSC_C11_C12, CNVC_CFG, id), \
125 SRI(PRE_CSC_C33_C34, CNVC_CFG, id), \
126 SRI(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
127 SRI(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
128 SRI(CM_POST_CSC_CONTROL, CM, id), \
129 SRI(CM_POST_CSC_C11_C12, CM, id), \
130 SRI(CM_POST_CSC_C33_C34, CM, id), \
131 SRI(CM_POST_CSC_B_C11_C12, CM, id), \
132 SRI(CM_POST_CSC_B_C33_C34, CM, id), \
133 SRI(CM_MEM_PWR_CTRL, CM, id), \
134 SRI(CM_CONTROL, CM, id), \
135 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
136 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
137 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
138 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
139 SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
140 SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
141 SRI(DPP_CONTROL, DPP_TOP, id), \
142 SRI(CM_HDR_MULT_COEF, CM, id), \
143 SRI(CURSOR_CONTROL, CURSOR0_, id), \
144 SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
145 SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
146 SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \
147 SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \
148 SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \
149 SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \
150 SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \
151 SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
152 SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
153 SRI(COLOR_KEYER_RED, CNVC_CFG, id), \
154 SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
155 SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
156 SRI(CURSOR_CONTROL, CURSOR0_, id),\
157 SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
158 SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
159 SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
161 #define DPP_REG_LIST_DCN30(id)\
162 DPP_REG_LIST_DCN30_COMMON(id), \
163 TF_REG_LIST_DCN20_COMMON(id), \
164 SRI(CM_BLNDGAM_CONTROL, CM, id), \
165 SRI(CM_SHAPER_LUT_DATA, CM, id),\
166 SRI(CM_MEM_PWR_CTRL2, CM, id), \
167 SRI(CM_MEM_PWR_STATUS2, CM, id), \
168 SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
169 SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
170 SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
171 SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\
172 SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\
173 SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
174 SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)