amd/amdgpu/vega10_ih.c

41  * vega10_ih_init_register_offset - Initialize register offset for ih rings
45  * Initialize register offset ih rings (VEGA10).
51 	if (adev->irq.ih.ring_size) {
52 		ih_regs = &adev->irq.ih.ih_regs;
91  * @ih: amdgpu_ih_ring pointet
97 					    struct amdgpu_ih_ring *ih,
103 	ih_regs = &ih->ih_regs;
109 	if (ih == &adev->irq.ih)
121 		ih->enabled = true;
126 		ih->enabled = false;
127 		ih->rptr = 0;
143 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
147 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
148 		if (ih[i]->ring_size) {
149 			r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable);
158 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
160 	int rb_bufsz = order_base_2(ih->ring_size / 4);
163 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);
181 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
185 	if (ih->use_doorbell) {
188 						 ih->doorbell_index);
201  * vega10_ih_enable_ring - enable an ih ring buffer
204  * @ih: amdgpu_ih_ring pointer
206  * Enable an ih ring buffer (VEGA10)
209 				 struct amdgpu_ih_ring *ih)
214 	ih_regs = &ih->ih_regs;
217 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
218 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
221 	tmp = vega10_ih_rb_cntl(ih, tmp);
222 	if (ih == &adev->irq.ih)
224 	if (ih == &adev->irq.ih1)
235 	if (ih == &adev->irq.ih) {
236 		/* set the ih ring 0 writeback address whether it's enabled or not */
237 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
238 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
245 	WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));
263 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
277 		if (adev->irq.ih.use_bus_addr) {
284 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
285 		if (ih[i]->ring_size) {
286 			ret = vega10_ih_enable_ring(adev, ih[i]);
293 		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
294 						    adev->irq.ih.doorbell_index);
328  * @ih: IH ring buffer to fetch wptr
336 			      struct amdgpu_ih_ring *ih)
341 	if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
347 		wptr = le32_to_cpu(*ih->wptr_cpu);
353 	ih_regs = &ih->ih_regs;
366 	tmp = (wptr + 32) & ih->ptr_mask;
369 		 wptr, ih->rptr, tmp);
370 	ih->rptr = tmp;
383 	return (wptr & ih->ptr_mask);
390  * @ih: IH ring to match
394 			       struct amdgpu_ih_ring *ih)
400 	ih_regs = &ih->ih_regs;
404 		if ((v < ih->ring_size) && (v != ih->rptr))
405 			WDOORBELL32(ih->doorbell_index, ih->rptr);
415  * @ih: IH ring buffer to set rptr
420 			       struct amdgpu_ih_ring *ih)
424 	if (ih == &adev->irq.ih_soft)
427 	if (ih->use_doorbell) {
429 		*ih->rptr_cpu = ih->rptr;
430 		WDOORBELL32(ih->doorbell_index, ih->rptr);
433 			vega10_ih_irq_rearm(adev, ih);
435 		ih_regs = &ih->ih_regs;
436 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
494 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true);
498 	adev->irq.ih.use_doorbell = true;
499 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
507 		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
514 		adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
516 	/* initialize ih control registers offset */