amd/amdgpu/vcn_v4_0_3.c

110 		volatile struct amdgpu_vcn4_fw_shared *fw_shared;
134 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
135 		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
136 		fw_shared->sq.is_enabled = true;
176 			volatile struct amdgpu_vcn4_fw_shared *fw_shared;
178 			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
179 			fw_shared->present_flag_0 = 0;
180 			fw_shared->sq.is_enabled = cpu_to_le32(false);
386 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
389 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
493 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
496 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
716 	volatile struct amdgpu_vcn4_fw_shared *fw_shared =
717 						adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
830 	fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
840 	fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
843 	fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
873 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
953 		fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
954 		rb_setup = &fw_shared->rb_setup;
964 		fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
968 			lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
971 			upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
1044 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1179 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1204 		fw_shared->sq.queue_mode &=
1252 	volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1259 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1260 		fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;