Lines Matching defs:dclk
1698 * @dclk: wanted DCLK
1708 * @optimal_dclk_div: resulting dclk post divider
1714 unsigned vclk, unsigned dclk,
1729 vco_min = max(max(vco_min, vclk), dclk);
1748 /* Calc dclk divider with current vco freq */
1749 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk,
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
1775 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1780 /* Bypass vclk and dclk with bclk */
1788 if (!vclk || !dclk) {
1793 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,