amd/amdgpu/navi10_ih.c

43  * navi10_ih_init_register_offset - Initialize register offset for ih rings
47  * Initialize register offset ih rings (NAVI10).
53 	if (adev->irq.ih.ring_size) {
54 		ih_regs = &adev->irq.ih.ih_regs;
147  * @ih: amdgpu_ih_ring pointet
153 					    struct amdgpu_ih_ring *ih,
159 	ih_regs = &ih->ih_regs;
165 	if (ih == &adev->irq.ih)
176 		ih->enabled = true;
181 		ih->enabled = false;
182 		ih->rptr = 0;
198 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
202 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
203 		if (ih[i]->ring_size) {
204 			r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable);
213 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
215 	int rb_bufsz = order_base_2(ih->ring_size / 4);
218 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);
236 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
240 	if (ih->use_doorbell) {
243 						 ih->doorbell_index);
256  * navi10_ih_enable_ring - enable an ih ring buffer
259  * @ih: amdgpu_ih_ring pointer
261  * Enable an ih ring buffer (NAVI10)
264 				 struct amdgpu_ih_ring *ih)
269 	ih_regs = &ih->ih_regs;
272 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
273 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
276 	tmp = navi10_ih_rb_cntl(ih, tmp);
277 	if (ih == &adev->irq.ih)
279 	if (ih == &adev->irq.ih1)
291 	if (ih == &adev->irq.ih) {
292 		/* set the ih ring 0 writeback address whether it's enabled or not */
293 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
294 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
301 	WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
319 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
332 		if (ih[0]->use_bus_addr) {
352 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
353 		if (ih[i]->ring_size) {
354 			ret = navi10_ih_enable_ring(adev, ih[i]);
360 	/* update doorbell range for ih ring 0*/
361 	adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
362 					    ih[0]->doorbell_index);
399  * @ih: IH ring buffer to fetch wptr
407 			      struct amdgpu_ih_ring *ih)
412 	if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
418 		wptr = le32_to_cpu(*ih->wptr_cpu);
424 	ih_regs = &ih->ih_regs;
436 	tmp = (wptr + 32) & ih->ptr_mask;
439 		 wptr, ih->rptr, tmp);
440 	ih->rptr = tmp;
452 	return (wptr & ih->ptr_mask);
459  * @ih: IH ring to match
463 			       struct amdgpu_ih_ring *ih)
469 	ih_regs = &ih->ih_regs;
474 		if ((v < ih->ring_size) && (v != ih->rptr))
475 			WDOORBELL32(ih->doorbell_index, ih->rptr);
486  * @ih: IH ring buffer to set rptr
490 			       struct amdgpu_ih_ring *ih)
494 	if (ih == &adev->irq.ih_soft)
497 	if (ih->use_doorbell) {
499 		*ih->rptr_cpu = ih->rptr;
500 		WDOORBELL32(ih->doorbell_index, ih->rptr);
503 			navi10_ih_irq_rearm(adev, ih);
505 		ih_regs = &ih->ih_regs;
506 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
566 	/* use gpu virtual address for ih ring
568 	 * use bus address for ih ring by psp bl */
574 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
578 	adev->irq.ih.use_doorbell = true;
579 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
584 	/* initialize ih control registers offset */