amd/amdgpu/mes_v10_1.c

631 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
635 	memset(mqd, 0, sizeof(*mqd));
637 	mqd->header = 0xC0310800;
638 	mqd->compute_pipelinestat_enable = 0x00000001;
639 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
640 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
641 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
642 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
643 	mqd->compute_misc_reserved = 0x00000003;
652 	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
653 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
654 	mqd->cp_hqd_eop_control = tmp;
658 	mqd->cp_hqd_pq_rptr = 0;
659 	mqd->cp_hqd_pq_wptr_lo = 0;
660 	mqd->cp_hqd_pq_wptr_hi = 0;
663 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
664 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
669 	mqd->cp_mqd_control = tmp;
673 	mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
674 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
678 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
679 	mqd->cp_hqd_pq_rptr_report_addr_hi =
684 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
685 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
701 	mqd->cp_hqd_pq_control = tmp;
718 	mqd->cp_hqd_pq_doorbell_control = tmp;
720 	mqd->cp_hqd_vmid = 0;
722 	mqd->cp_hqd_active = 1;
723 	mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT;
724 	mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT;
725 	mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT;
726 	mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT;
731 	mqd->cp_hqd_suspend_cntl_stack_offset = tmp;
740 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
759 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
760 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
768 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
769 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
773 		     mqd->cp_hqd_pq_rptr_report_addr_lo);
775 		     mqd->cp_hqd_pq_rptr_report_addr_hi);
778 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
782 		     mqd->cp_hqd_pq_wptr_poll_addr_lo);
784 		     mqd->cp_hqd_pq_wptr_poll_addr_hi);
788 		     mqd->cp_hqd_pq_doorbell_control);
791 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
794 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
905 		dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);