Lines Matching refs:mes
89 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
97 struct amdgpu_device *adev = mes->adev;
98 struct amdgpu_ring *ring = &mes->ring;
103 spin_lock_irqsave(&mes->ring_lock, flags);
105 spin_unlock_irqrestore(&mes->ring_lock, flags);
110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
115 spin_unlock_irqrestore(&mes->ring_lock, flags);
147 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
150 struct amdgpu_device *adev = mes->adev;
184 return mes_v10_1_submit_pkt_and_poll_completion(mes,
189 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes,
203 return mes_v10_1_submit_pkt_and_poll_completion(mes,
208 static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes,
237 return mes_v10_1_submit_pkt_and_poll_completion(mes,
242 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes,
248 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes,
254 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes)
264 return mes_v10_1_submit_pkt_and_poll_completion(mes,
269 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes)
272 struct amdgpu_device *adev = mes->adev;
281 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
282 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
285 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
287 mes->query_status_fence_gpu_addr;
291 mes->compute_hqd_mask[i];
294 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
297 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
301 mes->aggregated_doorbells[i];
315 return mes_v10_1_submit_pkt_and_poll_completion(mes,
320 static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes)
322 struct amdgpu_device *adev = mes->adev;
329 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
338 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
347 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
356 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
365 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
391 adev->mes.fw[pipe]->data;
393 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
399 &adev->mes.ucode_fw_obj[pipe],
400 &adev->mes.ucode_fw_gpu_addr[pipe],
401 (void **)&adev->mes.ucode_fw_ptr[pipe]);
403 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
407 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
409 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
410 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
424 adev->mes.fw[pipe]->data;
426 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
432 &adev->mes.data_fw_obj[pipe],
433 &adev->mes.data_fw_gpu_addr[pipe],
434 (void **)&adev->mes.data_fw_ptr[pipe]);
436 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
440 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
442 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
443 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
451 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
452 &adev->mes.data_fw_gpu_addr[pipe],
453 (void **)&adev->mes.data_fw_ptr[pipe]);
455 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
456 &adev->mes.ucode_fw_gpu_addr[pipe],
457 (void **)&adev->mes.ucode_fw_ptr[pipe]);
479 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2);
519 if (!adev->mes.fw[pipe])
540 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2);
544 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
546 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
553 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
555 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
613 &adev->mes.eop_gpu_obj[pipe],
614 &adev->mes.eop_gpu_addr[pipe],
621 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
623 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
624 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
816 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
825 r = mes_v10_1_mqd_init(&adev->mes.ring);
840 ring = &adev->mes.ring;
851 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
875 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
893 ring = &adev->mes.ring;
911 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
912 if (!adev->mes.mqd_backup[pipe]) {
927 adev->mes.funcs = &mes_v10_1_funcs;
928 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init;
965 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
966 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
969 kfree(adev->mes.mqd_backup[pipe]);
971 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
972 &adev->mes.eop_gpu_addr[pipe],
974 amdgpu_ucode_release(&adev->mes.fw[pipe]);
981 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
982 &adev->mes.ring.mqd_gpu_addr,
983 &adev->mes.ring.mqd_ptr);
986 amdgpu_ring_fini(&adev->mes.ring);
1076 r = mes_v10_1_set_hw_resources(&adev->mes);
1080 mes_v10_1_init_aggregated_doorbell(&adev->mes);
1082 r = mes_v10_1_query_sched_status(&adev->mes);
1094 adev->mes.ring.sched.ready = true;
1107 adev->mes.ring.sched.ready = false;