amd/amdgpu/hdp_v4_0.c

40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
44 		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
46 		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
49 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
52 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0) ||
53 	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2))
63 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
71 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
78 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
80 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
83 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) >= IP_VERSION(4, 4, 0))
90 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
95 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 0) ||
96 	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 0, 1) ||
97 	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 1) ||
98 	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 1, 0)) {
101 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
111 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
127 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
132 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2)) {
143 static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
145 	switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
154 	if (amdgpu_sriov_vf(adev))
159 	if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))
162 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
163 	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));