Lines Matching refs:vmid
92 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
93 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
122 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
153 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
998 /* Enable trap for each kfd vmid. */
1018 int vmid;
1026 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
1027 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
1028 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
1029 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
1030 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
1179 /* init spm vmid with 0xf */
1393 unsigned vmid)
1404 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1603 /* set MQD vmid to 0 */
1643 /* set the vmid for the queue */
1715 /* set MQD vmid to 0 */
1766 /* set the vmid for the queue */
2214 uint32_t vmid,
2223 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2228 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2233 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2238 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2582 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2583 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2658 unsigned vmid, uint64_t pd_addr)
2660 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);