amd/amdgpu/amdgpu_ras_eeprom.c

69 /* Table hdr is 'AMDR' */
233 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
238 	pp[0] = cpu_to_le32(hdr->header);
239 	pp[1] = cpu_to_le32(hdr->version);
240 	pp[2] = cpu_to_le32(hdr->first_rec_offset);
241 	pp[3] = cpu_to_le32(hdr->tbl_size);
242 	pp[4] = cpu_to_le32(hdr->checksum);
246 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
251 	hdr->header	      = le32_to_cpu(pp[0]);
252 	hdr->version	      = le32_to_cpu(pp[1]);
253 	hdr->first_rec_offset = le32_to_cpu(pp[2]);
254 	hdr->tbl_size	      = le32_to_cpu(pp[3]);
255 	hdr->checksum	      = le32_to_cpu(pp[4]);
386 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
391 	csum = -hdr->checksum;
393 	hh = (void *) &hdr->header;
399 	hdr->header = header;
400 	hdr->checksum = csum;
410 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
415 		hdr->version = RAS_TABLE_VER_V2_1;
418 		hdr->version = RAS_TABLE_VER_V1;
433 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
441 	hdr->header = RAS_TABLE_HDR_VAL;
444 	if (hdr->version == RAS_TABLE_VER_V2_1) {
445 		hdr->first_rec_offset = RAS_RECORD_START_V2_1;
446 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
457 		hdr->first_rec_offset = RAS_RECORD_START;
458 		hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
462 	if (hdr->version == RAS_TABLE_VER_V2_1)
465 	hdr->checksum = csum;
467 	if (!res && hdr->version > RAS_TABLE_VER_V1)
1327 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1356 	__decode_table_header_from_buf(hdr, buf);
1358 	if (hdr->version == RAS_TABLE_VER_V2_1) {
1359 		control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);
1363 		control->ras_num_recs = RAS_NUM_RECS(hdr);
1367 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1369 	if (hdr->header == RAS_TABLE_HDR_VAL) {
1373 		if (hdr->version == RAS_TABLE_VER_V2_1) {
1390 	} else if (hdr->header == RAS_TABLE_HDR_BAD &&
1392 		if (hdr->version == RAS_TABLE_VER_V2_1) {