amd/amdgpu/amdgpu_display.c

652 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
654 	if (!IS_AMD_FMT_MOD(modifier))
657 	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
662 	if (AMD_FMT_MOD_GET(DCC, modifier))
724 	uint64_t modifier = 0;
732 		modifier = DRM_FORMAT_MOD_LINEAR;
828 		modifier = AMD_FMT_MOD |
853 			modifier |= AMD_FMT_MOD_SET(DCC, 1) |
867 			 * but we should convert it to a modifier plane for getfb2, so the
878 				modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
892 					modifier |= AMD_FMT_MOD_SET(RB, rb) |
902 								modifier);
910 	afb->base.modifier = modifier;
949 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
952 	unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
961 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
966 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
969 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
1033 	uint64_t modifier = rfb->base.modifier;
1041 		if (modifier == DRM_FORMAT_MOD_LINEAR) {
1046 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1080 	if (AMD_FMT_MOD_GET(DCC, modifier)) {
1081 		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1082 			block_size_log2 = get_dcc_block_size(modifier, false, false);
1092 			block_size_log2 = get_dcc_block_size(modifier, true, true);
1094 			bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1096 			block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1152 	/* Verify that the modifier is supported. */
1154 				      mode_cmd->modifier[0])) {
1156 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
1157 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1192 	 * This needs to happen before modifier conversion as that might change
1210 			      "GFX9+ requires FB check based on format modifier\n");
1220 			drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",