amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

45 			uint32_t queue, uint32_t vmid)
48 	nv_grbm_select(adev, mec, pipe, queue, vmid);
80 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
86 	lock_srbm(adev, 0, 0, 0, vmid);
96 					unsigned int vmid, uint32_t inst)
108 	pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
110 	pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
111 	WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
119 		 (1U << vmid)))
125 	       1U << vmid);
128 	/* Mapping vmid to pasid also for IH block */
130 	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
666 					uint8_t vmid, uint16_t *p_pasid)
671 		     + vmid);
702 		uint32_t vmid, uint64_t page_table_base)
704 	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
706 		       vmid);
711 	adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
717  * vmid:
736 static void kgd_gfx_v10_set_wave_launch_stall(struct amdgpu_device *adev, uint32_t vmid, bool stall)
742 							stall ? 1 << vmid : 0);
755 				uint32_t vmid)
760 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
767 				VMID_SEL, 1 << vmid);
774 		kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
783 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
792 					uint32_t vmid)
796 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
800 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
826 					      uint32_t vmid,
839 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
861 					uint32_t vmid)
868 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, true);
871 			VMID_MASK, is_mode_set ? 1 << vmid : 0);
876 	kgd_gfx_v10_set_wave_launch_stall(adev, vmid, false);
1048 		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
1051 	lock_srbm(adev, 0, 0, 0, vmid);