Lines Matching refs:bank
76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
79 void __iomem *reg = bank->reg_base + offset;
81 if (bank->gpio_type == GPIO_TYPE_V2)
87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
90 void __iomem *reg = bank->reg_base + offset;
93 if (bank->gpio_type == GPIO_TYPE_V2)
101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
105 void __iomem *reg = bank->reg_base + offset;
108 if (bank->gpio_type == GPIO_TYPE_V2) {
123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
126 void __iomem *reg = bank->reg_base + offset;
129 if (bank->gpio_type == GPIO_TYPE_V2) {
143 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
146 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
156 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
166 raw_spin_lock_irqsave(&bank->slock, flags);
167 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
168 raw_spin_unlock_irqrestore(&bank->slock, flags);
176 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
179 raw_spin_lock_irqsave(&bank->slock, flags);
180 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
181 raw_spin_unlock_irqrestore(&bank->slock, flags);
186 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
189 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
200 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
201 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
207 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
209 freq = clk_get_rate(bank->db_clk);
220 raw_spin_lock_irqsave(&bank->slock, flags);
226 cur_div_reg = readl(bank->reg_base +
229 writel(div_reg, bank->reg_base +
231 rockchip_gpio_writel_bit(bank, offset, 1,
235 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
238 rockchip_gpio_writel_bit(bank, offset, 0,
241 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
244 raw_spin_unlock_irqrestore(&bank->slock, flags);
249 clk_prepare_enable(bank->db_clk);
251 clk_disable_unprepare(bank->db_clk);
307 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
310 if (!bank->domain)
313 virq = irq_create_mapping(bank->domain, offset);
334 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
338 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
342 pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
344 dev_dbg(bank->dev, "handling irq %d\n", irq);
350 if (bank->toggle_edge_mode & BIT(irq)) {
354 data = readl_relaxed(bank->reg_base +
355 bank->gpio_regs->ext_port);
357 raw_spin_lock_irqsave(&bank->slock, flags);
359 polarity = readl_relaxed(bank->reg_base +
360 bank->gpio_regs->int_polarity);
366 bank->reg_base +
367 bank->gpio_regs->int_polarity);
369 raw_spin_unlock_irqrestore(&bank->slock, flags);
372 data = readl_relaxed(bank->reg_base +
373 bank->gpio_regs->ext_port);
377 generic_handle_domain_irq(bank->domain, irq);
386 struct rockchip_pin_bank *bank = gc->private;
394 raw_spin_lock_irqsave(&bank->slock, flags);
396 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
397 bank->gpio_regs->port_ddr);
399 raw_spin_unlock_irqrestore(&bank->slock, flags);
406 raw_spin_lock_irqsave(&bank->slock, flags);
408 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
409 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
412 if (bank->gpio_type == GPIO_TYPE_V2) {
413 rockchip_gpio_writel_bit(bank, d->hwirq, 1,
414 bank->gpio_regs->int_bothedge);
417 bank->toggle_edge_mode |= mask;
424 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
431 if (bank->gpio_type == GPIO_TYPE_V2) {
432 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
433 bank->gpio_regs->int_bothedge);
435 bank->toggle_edge_mode &= ~mask;
460 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
461 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
463 raw_spin_unlock_irqrestore(&bank->slock, flags);
471 struct rockchip_pin_bank *bank = gc->private;
473 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
479 struct rockchip_pin_bank *bank = gc->private;
481 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
487 struct rockchip_pin_bank *bank = gc->private;
489 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
490 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
496 struct rockchip_pin_bank *bank = gc->private;
498 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
511 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
517 bank->domain = irq_domain_add_linear(bank->of_node, 32,
519 if (!bank->domain) {
520 dev_warn(bank->dev, "could not init irq domain for bank %s\n",
521 bank->name);
525 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
530 dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
531 bank->name);
532 irq_domain_remove(bank->domain);
536 gc = irq_get_domain_generic_chip(bank->domain, 0);
537 if (bank->gpio_type == GPIO_TYPE_V2) {
542 gc->reg_base = bank->reg_base;
543 gc->private = bank;
544 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
545 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
557 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
564 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
565 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
566 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
569 irq_set_chained_handler_and_data(bank->irq,
570 rockchip_irq_demux, bank);
575 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
580 bank->gpio_chip = rockchip_gpiolib_chip;
582 gc = &bank->gpio_chip;
583 gc->base = bank->pin_base;
584 gc->ngpio = bank->nr_pins;
585 gc->label = bank->name;
586 gc->parent = bank->dev;
588 ret = gpiochip_add_data(gc, bank);
590 dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
605 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
606 struct device_node *pctlnp = of_get_parent(bank->of_node);
620 dev_err(bank->dev, "Failed to add pin range\n");
625 ret = rockchip_interrupts_register(bank);
627 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
634 gpiochip_remove(&bank->gpio_chip);
639 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
644 if (of_address_to_resource(bank->of_node, 0, &res)) {
645 dev_err(bank->dev, "cannot find IO resource for bank\n");
649 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
650 if (IS_ERR(bank->reg_base))
651 return PTR_ERR(bank->reg_base);
653 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
654 if (!bank->irq)
657 bank->clk = of_clk_get(bank->of_node, 0);
658 if (IS_ERR(bank->clk))
659 return PTR_ERR(bank->clk);
661 clk_prepare_enable(bank->clk);
662 id = readl(bank->reg_base + gpio_regs_v2.version_id);
666 bank->gpio_regs = &gpio_regs_v2;
667 bank->gpio_type = GPIO_TYPE_V2;
668 bank->db_clk = of_clk_get(bank->of_node, 1);
669 if (IS_ERR(bank->db_clk)) {
670 dev_err(bank->dev, "cannot find debounce clk\n");
671 clk_disable_unprepare(bank->clk);
675 bank->gpio_regs = &gpio_regs_v1;
676 bank->gpio_type = GPIO_TYPE_V1;
686 struct rockchip_pin_bank *bank;
690 bank = info->ctrl->pin_banks;
691 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
692 if (bank->bank_num == id) {
698 return found ? bank : NULL;
707 struct rockchip_pin_bank *bank = NULL;
723 bank = rockchip_gpio_find_bank(pctldev, id);
724 if (!bank)
727 bank->dev = dev;
728 bank->of_node = np;
730 raw_spin_lock_init(&bank->slock);
732 ret = rockchip_get_bank_data(bank);
740 mutex_lock(&bank->deferred_lock);
742 ret = rockchip_gpiolib_register(bank);
744 clk_disable_unprepare(bank->clk);
745 mutex_unlock(&bank->deferred_lock);
749 while (!list_empty(&bank->deferred_pins)) {
750 cfg = list_first_entry(&bank->deferred_pins,
756 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
762 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin);
773 mutex_unlock(&bank->deferred_lock);
775 platform_set_drvdata(pdev, bank);
783 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
785 clk_disable_unprepare(bank->clk);
786 gpiochip_remove(&bank->gpio_chip);
790 { .compatible = "rockchip,gpio-bank", },