Lines Matching refs:signals
14 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
19 * and the number of incoming DMA signals are two totally different things.
20 * It is usually not possible to theoretically handle all physical signals,
46 * signals, the DMA controller will simply facilitate its AHB master.)
54 * to both the BREQ and SREQ signals (contrary to documented),
55 * transferring data if either is active. The LBREQ and LSREQ signals
100 * @signals: the number of request signals available from the hardware
114 u8 signals;
266 * @has_slave: the PL08x has a slave engine (routed signals)
1729 * synchronization of slave DMA signals with the DMAC enable
2386 * Some implementations have muxed signals, whereas some
2387 * use a mux in front of the signals and need dynamic
2388 * assignment of signals.
2660 if (pl08x->vd->signals) {
2662 pl08x->vd->signals,
2669 for (i = 0; i < pl08x->vd->signals; i++) {
2676 pd->num_slave_channels = pl08x->vd->signals;
2771 * Initialize slave engine, if the block has no signals, that means
2774 if (vd->signals) {
2985 .signals = 16,
2993 .signals = 32,
3002 .signals = 32,
3010 .signals = 16,