drivers/dma/amba-pl08x.c

369 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
374 	if (ch->reg_busy) {
375 		val = readl(ch->reg_busy);
376 		return !!(val & BIT(ch->id));
378 	val = readl(ch->reg_config);
582 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
587 	if (ch->ftdmac020) {
589 		val = readl(ch->reg_control);
591 		writel(val, ch->reg_control);
596 	val = readl(ch->reg_config);
598 	writel(val, ch->reg_config);
602 		if (!pl08x_phy_channel_busy(ch))
606 	if (pl08x_phy_channel_busy(ch))
607 		pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
610 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
615 	if (ch->ftdmac020) {
616 		val = readl(ch->reg_control);
618 		writel(val, ch->reg_control);
623 	val = readl(ch->reg_config);
625 	writel(val, ch->reg_config);
635 	struct pl08x_phy_chan *ch)
640 	if (ch->ftdmac020) {
642 		val = readl(ch->reg_config);
646 		writel(val, ch->reg_config);
649 		val = readl(ch->reg_control);
652 		writel(val, ch->reg_control);
655 		writel(BIT(ch->id) | BIT(ch->id + 16),
657 		writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
662 	val = readl(ch->reg_config);
665 	writel(val, ch->reg_config);
667 	writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
668 	writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
671 static u32 get_bytes_in_phy_channel(struct pl08x_phy_chan *ch)
676 	if (ch->ftdmac020) {
677 		bytes = readl(ch->base + FTDMAC020_CH_SIZE);
679 		val = readl(ch->reg_control);
682 	} else if (ch->pl080s) {
683 		val = readl(ch->base + PL080S_CH_CONTROL2);
686 		val = readl(ch->reg_control);
691 		val = readl(ch->reg_control);
711 static u32 get_bytes_in_lli(struct pl08x_phy_chan *ch, const u32 *llis_va)
716 	if (ch->ftdmac020) {
723 	} else if (ch->pl080s) {
757 	struct pl08x_phy_chan *ch;
764 	ch = plchan->phychan;
767 	if (!ch || !txd)
774 	clli = readl(ch->reg_lli) & ~PL080_LLI_LM_AHB2;
777 	bytes = get_bytes_in_phy_channel(ch);
798 		bytes += get_bytes_in_lli(ch, llis_va);
821 	struct pl08x_phy_chan *ch = NULL;
826 		ch = &pl08x->phy_chans[i];
828 		spin_lock_irqsave(&ch->lock, flags);
830 		if (!ch->locked && !ch->serving) {
831 			ch->serving = virt_chan;
832 			spin_unlock_irqrestore(&ch->lock, flags);
836 		spin_unlock_irqrestore(&ch->lock, flags);
844 	return ch;
849 					 struct pl08x_phy_chan *ch)
851 	ch->serving = NULL;
862 	struct pl08x_phy_chan *ch;
864 	ch = pl08x_get_phy_channel(pl08x, plchan);
865 	if (!ch) {
873 		ch->id, plchan->name);
875 	plchan->phychan = ch;
880 static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
886 		ch->id, plchan->name);
893 	ch->serving = plchan;
894 	plchan->phychan = ch;
2453 	struct pl08x_phy_chan *ch;
2463 		ch = &pl08x->phy_chans[i];
2465 		spin_lock_irqsave(&ch->lock, flags);
2466 		virt_chan = ch->serving;
2469 			   ch->id,
2471 			   ch->locked ? " LOCKED" : "");
2473 		spin_unlock_irqrestore(&ch->lock, flags);
2866 		struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2868 		ch->id = i;
2869 		ch->base = pl08x->base + PL080_Cx_BASE(i);
2872 			ch->reg_busy = ch->base + FTDMAC020_CH_BUSY;
2873 			ch->reg_config = ch->base + FTDMAC020_CH_CFG;
2874 			ch->reg_control = ch->base + FTDMAC020_CH_CSR;
2875 			ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR;
2876 			ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR;
2877 			ch->reg_lli = ch->base + FTDMAC020_CH_LLP;
2878 			ch->ftdmac020 = true;
2880 			ch->reg_config = ch->base + vd->config_offset;
2881 			ch->reg_control = ch->base + PL080_CH_CONTROL;
2882 			ch->reg_src = ch->base + PL080_CH_SRC_ADDR;
2883 			ch->reg_dst = ch->base + PL080_CH_DST_ADDR;
2884 			ch->reg_lli = ch->base + PL080_CH_LLI;
2887 			ch->pl080s = true;
2889 		spin_lock_init(&ch->lock);
2899 			val = readl(ch->reg_config);
2902 				ch->locked = true;
2907 			i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");