hisilicon/zip/zip_main.c

478 	val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);
485 	writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);
486 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET,
504 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
506 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);
508 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,
523 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
525 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);
527 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,
541 	val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL);
543 	writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);
545 	val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
547 	writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
552 	void __iomem *base = qm->io_base;
609 	val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
620 		writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);
622 	writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
631 		       qm->io_base + HZIP_CORE_INT_MASK_REG);
640 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);
643 	writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
644 	writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
645 	writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
650 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
660 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG);
674 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
685 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
687 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
835 		regset->base = qm->io_base + core_offsets[i];
927 	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
930 			readl(qm->io_base + core_offsets[i] +
934 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
956 	void __iomem *io_base;
968 		io_base = qm->io_base + hzip_com_dfx_regs[i].offset;
969 		debug->last_words[i] = readl_relaxed(io_base);
973 		io_base = qm->io_base + core_offsets[i];
977 				io_base + hzip_dump_dfx_regs[j].offset);
1010 		val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);
1025 		base = qm->io_base + core_offsets[i];
1052 				err_val = readl(qm->io_base +
1065 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);
1072 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
1074 	writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1081 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1084 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1087 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1095 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1097 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1101 	       qm->io_base + HZIP_CORE_INT_SET);