crypto/ccp/ccp-dev-v5.c

25 static u32 ccp_lsb_alloc(struct ccp_cmd_queue *cmd_q, unsigned int count)
31 	if (cmd_q->lsb >= 0) {
32 		start = (u32)bitmap_find_next_zero_area(cmd_q->lsbmap,
36 			bitmap_set(cmd_q->lsbmap, start, count);
37 			return start + cmd_q->lsb * LSB_SIZE;
42 	ccp = cmd_q->ccp;
70 static void ccp_lsb_free(struct ccp_cmd_queue *cmd_q, unsigned int start,
76 	if (cmd_q->lsb == start) {
78 		bitmap_clear(cmd_q->lsbmap, start, count);
81 		struct ccp_device *ccp = cmd_q->ccp;
207 static unsigned int ccp5_get_free_slots(struct ccp_cmd_queue *cmd_q)
212 	queue_start = low_address(cmd_q->qdma_tail);
213 	head_lo = ioread32(cmd_q->reg_head_lo);
216 	n = head_idx + COMMANDS_PER_QUEUE - cmd_q->qidx - 1;
222 		       struct ccp_cmd_queue *cmd_q)
230 	cmd_q->total_ops++;
236 	mutex_lock(&cmd_q->q_mutex);
238 	mP = (__le32 *)&cmd_q->qbase[cmd_q->qidx];
243 	cmd_q->qidx = (cmd_q->qidx + 1) % COMMANDS_PER_QUEUE;
249 	tail = low_address(cmd_q->qdma_tail + cmd_q->qidx * Q_DESC_SIZE);
250 	iowrite32(tail, cmd_q->reg_tail_lo);
253 	iowrite32(cmd_q->qcontrol | CMD5_Q_RUN, cmd_q->reg_control);
254 	mutex_unlock(&cmd_q->q_mutex);
258 		ret = wait_event_interruptible(cmd_q->int_queue,
259 					       cmd_q->int_rcvd);
260 		if (ret || cmd_q->cmd_error) {
264 			if (cmd_q->cmd_error)
265 				ccp_log_error(cmd_q->ccp,
266 					      cmd_q->cmd_error);
267 			iowrite32(tail, cmd_q->reg_head_lo);
271 		cmd_q->int_rcvd = 0;
283 	op->cmd_q->total_aes_ops++;
319 	return ccp5_do_cmd(&desc, op->cmd_q);
328 	op->cmd_q->total_xts_aes_ops++;
362 	return ccp5_do_cmd(&desc, op->cmd_q);
370 	op->cmd_q->total_sha_ops++;
403 	return ccp5_do_cmd(&desc, op->cmd_q);
412 	op->cmd_q->total_3des_ops++;
446 	return ccp5_do_cmd(&desc, op->cmd_q);
454 	op->cmd_q->total_rsa_ops++;
488 	return ccp5_do_cmd(&desc, op->cmd_q);
499 	op->cmd_q->total_pt_ops++;
549 	return ccp5_do_cmd(&desc, op->cmd_q);
557 	op->cmd_q->total_ecc_ops++;
584 	return ccp5_do_cmd(&desc, op->cmd_q);
587 static int ccp_find_lsb_regions(struct ccp_cmd_queue *cmd_q, u64 status)
589 	int q_mask = 1 << cmd_q->id;
598 			bitmap_set(cmd_q->lsbmask, j, 1);
601 	queues = bitmap_weight(cmd_q->lsbmask, MAX_LSB_CNT);
602 	dev_dbg(cmd_q->ccp->dev, "Queue %d can access %d LSB regions\n",
603 		 cmd_q->id, queues);
628 		struct ccp_cmd_queue *cmd_q = &ccp->cmd_q[i];
630 		qlsb_wgt = bitmap_weight(cmd_q->lsbmask, MAX_LSB_CNT);
633 			bitmap_copy(qlsb, cmd_q->lsbmask, MAX_LSB_CNT);
641 					cmd_q->lsb = bitno;
679 			  lsb_pub, ccp->cmd_q[i].lsbmask,
725 		iowrite32(0x0, ccp->cmd_q[i].reg_int_enable);
733 		iowrite32(SUPPORTED_INTERRUPTS, ccp->cmd_q[i].reg_int_enable);
743 		struct ccp_cmd_queue *cmd_q = &ccp->cmd_q[i];
745 		status = ioread32(cmd_q->reg_interrupt_status);
748 			cmd_q->int_status = status;
749 			cmd_q->q_status = ioread32(cmd_q->reg_status);
750 			cmd_q->q_int_status = ioread32(cmd_q->reg_int_status);
753 			if ((status & INT_ERROR) && !cmd_q->cmd_error)
754 				cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
756 			cmd_q->int_rcvd = 1;
759 			iowrite32(status, cmd_q->reg_interrupt_status);
760 			wake_up_interruptible(&cmd_q->int_queue);
782 	struct ccp_cmd_queue *cmd_q;
820 		cmd_q = &ccp->cmd_q[ccp->cmd_q_count];
823 		cmd_q->ccp = ccp;
824 		cmd_q->id = i;
825 		cmd_q->dma_pool = dma_pool;
826 		mutex_init(&cmd_q->q_mutex);
830 		cmd_q->qsize = Q_SIZE(Q_DESC_SIZE);
831 		cmd_q->qbase = dmam_alloc_coherent(dev, cmd_q->qsize,
832 						   &cmd_q->qbase_dma,
834 		if (!cmd_q->qbase) {
840 		cmd_q->qidx = 0;
844 		cmd_q->reg_control = ccp->io_regs +
846 		cmd_q->reg_tail_lo = cmd_q->reg_control + CMD5_Q_TAIL_LO_BASE;
847 		cmd_q->reg_head_lo = cmd_q->reg_control + CMD5_Q_HEAD_LO_BASE;
848 		cmd_q->reg_int_enable = cmd_q->reg_control +
850 		cmd_q->reg_interrupt_status = cmd_q->reg_control +
852 		cmd_q->reg_status = cmd_q->reg_control + CMD5_Q_STATUS_BASE;
853 		cmd_q->reg_int_status = cmd_q->reg_control +
855 		cmd_q->reg_dma_status = cmd_q->reg_control +
857 		cmd_q->reg_dma_read_status = cmd_q->reg_control +
859 		cmd_q->reg_dma_write_status = cmd_q->reg_control +
862 		init_waitqueue_head(&cmd_q->int_queue);
876 		cmd_q = &ccp->cmd_q[i];
878 		cmd_q->qcontrol = 0; /* Start with nothing */
879 		iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
881 		ioread32(cmd_q->reg_int_status);
882 		ioread32(cmd_q->reg_status);
885 		iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_interrupt_status);
914 		cmd_q = &ccp->cmd_q[i];
916 		cmd_q->qcontrol &= ~(CMD5_Q_SIZE << CMD5_Q_SHIFT);
917 		cmd_q->qcontrol |= QUEUE_SIZE_VAL << CMD5_Q_SHIFT;
919 		cmd_q->qdma_tail = cmd_q->qbase_dma;
920 		dma_addr_lo = low_address(cmd_q->qdma_tail);
921 		iowrite32((u32)dma_addr_lo, cmd_q->reg_tail_lo);
922 		iowrite32((u32)dma_addr_lo, cmd_q->reg_head_lo);
924 		dma_addr_hi = high_address(cmd_q->qdma_tail);
925 		cmd_q->qcontrol |= (dma_addr_hi << 16);
926 		iowrite32(cmd_q->qcontrol, cmd_q->reg_control);
929 		ccp_find_lsb_regions(cmd_q, status);
930 		cmd_q->lsb = -1; /* Unassigned value */
942 		ccp->cmd_q[i].sb_key = ccp_lsb_alloc(&ccp->cmd_q[i], 2);
943 		ccp->cmd_q[i].sb_ctx = ccp_lsb_alloc(&ccp->cmd_q[i], 2);
951 		cmd_q = &ccp->cmd_q[i];
953 		kthread = kthread_run(ccp_cmd_queue_thread, cmd_q,
954 				      "%s-q%u", ccp->name, cmd_q->id);
962 		cmd_q->kthread = kthread;
993 		if (ccp->cmd_q[i].kthread)
994 			kthread_stop(ccp->cmd_q[i].kthread);
1001 		dma_pool_destroy(ccp->cmd_q[i].dma_pool);
1008 	struct ccp_cmd_queue *cmd_q;
1032 		cmd_q = &ccp->cmd_q[i];
1035 		iowrite32(cmd_q->qcontrol & ~CMD5_Q_RUN, cmd_q->reg_control);
1038 		iowrite32(SUPPORTED_INTERRUPTS, cmd_q->reg_interrupt_status);
1039 		ioread32(cmd_q->reg_int_status);
1040 		ioread32(cmd_q->reg_status);
1045 		if (ccp->cmd_q[i].kthread)
1046 			kthread_stop(ccp->cmd_q[i].kthread);