Lines Matching refs:idx

27 #define UNIPHIER_LD4_SYS_CLK_NAND(idx)					\
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
31 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
35 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
39 #define UNIPHIER_SYS_CLK_NAND_4X(idx) \
40 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
42 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
45 #define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
48 #define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
51 #define UNIPHIER_LD11_SYS_CLK_HSC(idx) \
52 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
54 #define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
57 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
60 #define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
64 #define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \
66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
68 #define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
70 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
72 #define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
74 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
76 #define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
80 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
81 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
83 #define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
84 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
339 .idx = 0,