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c64daf36 |
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11-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: Add SoC-glue clock source selector support for Pro4 Add SoC-glue clock source selector for ahci controller on UniPhier SoCs. Currently this supports Pro4 only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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bed51629 |
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11-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: Add NX1 clock support Add basic clock data for UniPhier NX1 SoC. This includes PLL and clock division data for cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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4c4065c7 |
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11-Oct-2021 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: Add audio system and video input clock control for PXs3 Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on UniPhier PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c942fddf |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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ff388ee3 |
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18-Jul-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add clock frequency support for SPI Add clock control for SPI controller on UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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9d222574 |
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20-Jul-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add more USB3 PHY clocks Add USB3 PHY clocks where missing. Use fixed-factor clocks for those without gating. For clarification, prefix clock names with 'ss' or 'hs'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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0316c018 |
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20-Jul-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add NAND 200MHz clock The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c5fc9cf2 |
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14-May-2018 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
clk: uniphier: add LD11/LD20 stream demux system clock Add clock for MPEG2 transport stream I/O and demux system (HSC) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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6f1aa4ef |
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30-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add additional ethernet clock lines for Pro4 Pro4 SoC has clock lines for Giga-bit feature and ethernet phy, and these are mandatory to activate the ethernet controller. This adds support for the clock lines. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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54e1f7ee |
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30-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add SATA clock control support Add clock control for SATA controller on UniPhier SoCs. This adds support for PXs2, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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2e277efb |
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30-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add PCIe clock control support Add clock control for PCIe controller on UniPhier SoCs. This adds support for Pro5, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c2fd8756 |
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22-Mar-2018 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add ethernet clock control support for PXs3 Add clock control for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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afeb079b |
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08-Mar-2018 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
clk: uniphier: add Pro4/Pro5/PXs2 audio system clock Add clock for audio subsystem (AIO) on UniPhier Pro4/Pro5/PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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67affb78 |
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04-Oct-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: fix DAPLL2 clock rate of Pro5 The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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db9d79f6 |
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13-Oct-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: fix clock data for PXs3 Fix reg offsets of USB clocks. Fixes: 736de651a836 ("clk: uniphier: add PXs3 clock data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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6c264416 |
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10-Aug-2017 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
clk: uniphier: add video input subsystem clock Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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e3dd2058 |
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10-Aug-2017 |
Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> |
clk: uniphier: add audio system clock Add clock for audio subsystem (AIO) and SoC internal audio codec (EVEA) on UniPhier LD11/LD20 SoCs. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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736de651 |
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31-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add PXs3 clock data Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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9959989f |
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28-Aug-2017 |
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> |
clk: uniphier: add ethernet clock control support Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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e66d57a9 |
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25-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: remove sLD3 SoC support This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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72d0d867 |
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20-Jun-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: provide NAND controller clock rate This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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2a353221 |
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28-Jan-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add eMMC clock for LD11 and LD20 SoCs Add clock for the Cadence eMMC controller on LD11/LD20. For the other SoCs, the clock for the eMMC controller is included in the MIO/SD control block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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19771622 |
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28-Jan-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add NAND clock for all UniPhier SoCs Add clock line for the Denali NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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1221ae21 |
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06-Dec-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add cpufreq data for LD11, LD20 SoCs Add more data to 64bit SoCs for the cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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7f4d3b52 |
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16-Sep-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
clk: uniphier: add clock data for UniPhier SoCs Add clock data arrays for all UniPhier SoCs with a binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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