clk/spear/spear6xx_clock.c

118 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
119 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
121 	clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
122 	clk_register_clkdev(clk, "osc_30m_clk", NULL);
125 	clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
127 	clk_register_clkdev(clk, NULL, "rtc-spear");
130 	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
132 	clk_register_clkdev(clk, "pll3_clk", NULL);
134 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
136 			&_lock, &clk1, NULL);
137 	clk_register_clkdev(clk, "vco1_clk", NULL);
138 	clk_register_clkdev(clk1, "pll1_clk", NULL);
140 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
142 			&_lock, &clk1, NULL);
143 	clk_register_clkdev(clk, "vco2_clk", NULL);
144 	clk_register_clkdev(clk1, "pll2_clk", NULL);
146 	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
148 	clk_register_clkdev(clk, NULL, "fc880000.wdt");
151 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
153 	clk_register_clkdev(clk, "cpu_clk", NULL);
155 	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
158 	clk_register_clkdev(clk, "ahb_clk", NULL);
161 			UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
163 	clk_register_clkdev(clk, "uart_syn_clk", NULL);
164 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
166 	clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
170 	clk_register_clkdev(clk, "uart_mclk", NULL);
172 	clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
174 	clk_register_clkdev(clk, NULL, "d0000000.serial");
176 	clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
178 	clk_register_clkdev(clk, NULL, "d0080000.serial");
181 			0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
183 	clk_register_clkdev(clk, "firda_syn_clk", NULL);
184 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
186 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
190 	clk_register_clkdev(clk, "firda_mclk", NULL);
192 	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
194 	clk_register_clkdev(clk, NULL, "firda");
197 			0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
199 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
200 	clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
202 	clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
206 	clk_register_clkdev(clk, "clcd_mclk", NULL);
208 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
210 	clk_register_clkdev(clk, NULL, "fc200000.clcd");
215 	clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
217 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
220 	clk_register_clkdev(clk, NULL, "gpt0");
222 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
225 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
227 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
229 	clk_register_clkdev(clk, NULL, "gpt1");
233 	clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
235 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
238 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
240 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
242 	clk_register_clkdev(clk, NULL, "gpt2");
246 	clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
248 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
251 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
253 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
255 	clk_register_clkdev(clk, NULL, "gpt3");
258 	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
260 	clk_register_clkdev(clk, NULL, "e1800000.ehci");
261 	clk_register_clkdev(clk, NULL, "e1900000.ohci");
263 	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
265 	clk_register_clkdev(clk, NULL, "e2000000.ehci");
266 	clk_register_clkdev(clk, NULL, "e2100000.ohci");
268 	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
270 	clk_register_clkdev(clk, NULL, "designware_udc");
273 	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
275 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
277 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
280 	clk_register_clkdev(clk, "ddr_clk", NULL);
282 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
285 	clk_register_clkdev(clk, "apb_clk", NULL);
287 	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
289 	clk_register_clkdev(clk, NULL, "fc400000.dma");
291 	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
293 	clk_register_clkdev(clk, NULL, "d1800000.flash");
295 	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
297 	clk_register_clkdev(clk, NULL, "e0800000.ethernet");
299 	clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
301 	clk_register_clkdev(clk, NULL, "d0200000.i2c");
303 	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
305 	clk_register_clkdev(clk, NULL, "jpeg");
307 	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
309 	clk_register_clkdev(clk, NULL, "fc000000.flash");
312 	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
314 	clk_register_clkdev(clk, NULL, "d820b000.adc");
316 	clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
317 	clk_register_clkdev(clk, NULL, "f0100000.gpio");
319 	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
321 	clk_register_clkdev(clk, NULL, "fc980000.gpio");
323 	clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
325 	clk_register_clkdev(clk, NULL, "d8100000.gpio");
327 	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
329 	clk_register_clkdev(clk, NULL, "d0100000.spi");
331 	clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
333 	clk_register_clkdev(clk, NULL, "d0180000.spi");
335 	clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
337 	clk_register_clkdev(clk, NULL, "d8180000.spi");