clk/renesas/clk-div6.c

27  * struct div6_clock - CPG 6 bit divider clock
31  * @src_mask: Bitmask covering the register bits to select the parent clock
32  * @nb: Notifier block to save/restore clock state for system resume
48 	struct div6_clock *clock = to_div6_clock(hw);
51 	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
52 	    | CPG_DIV6_DIV(clock->div - 1);
53 	writel(val, clock->reg);
60 	struct div6_clock *clock = to_div6_clock(hw);
63 	val = readl(clock->reg);
67 	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
69 	 * clock
73 	writel(val, clock->reg);
78 	struct div6_clock *clock = to_div6_clock(hw);
80 	return !(readl(clock->reg) & CPG_DIV6_CKSTP);
86 	struct div6_clock *clock = to_div6_clock(hw);
88 	return parent_rate / clock->div;
151 	struct div6_clock *clock = to_div6_clock(hw);
155 	clock->div = div;
157 	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
158 	/* Only program the new divisor if the clock isn't stopped. */
160 		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
167 	struct div6_clock *clock = to_div6_clock(hw);
171 	if (clock->src_mask == 0)
174 	hw_index = (readl(clock->reg) & clock->src_mask) >>
175 		   __ffs(clock->src_mask);
177 		if (clock->parents[i] == hw_index)
181 	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
188 	struct div6_clock *clock = to_div6_clock(hw);
194 	src = clock->parents[index] << __ffs(clock->src_mask);
195 	writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
213 	struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
224 		if (__clk_get_enable_count(clock->hw.clk))
225 			cpg_div6_clock_enable(&clock->hw);
227 			cpg_div6_clock_disable(&clock->hw);
235  * cpg_div6_register - Register a DIV6 clock
236  * @name: Name of the DIV6 clock
237  * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
239  * @reg: Mapped register used to control the DIV6 clock
250 	struct div6_clock *clock;
254 	clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
255 	if (!clock)
258 	clock->reg = reg;
261 	 * Read the divisor. Disabling the clock overwrites the divisor, so we
264 	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
268 		/* fixed parent clock */
269 		clock->src_mask = 0;
272 		/* clock with EXSRC bits 6-7 */
273 		clock->src_mask = GENMASK(7, 6);
277 		clock->src_mask = GENMASK(14, 12);
280 		pr_err("%s: invalid number of parents for DIV6 clock %s\n",
290 			clock->parents[valid_parents] = i;
295 	/* Register the clock. */
301 	clock->hw.init = &init;
303 	clk = clk_register(NULL, &clock->hw);
308 		clock->nb.notifier_call = cpg_div6_clock_notifier_call;
309 		raw_notifier_chain_register(notifiers, &clock->nb);
315 	kfree(clock);
330 		pr_err("%s: no parent found for %pOFn DIV6 clock\n",
342 		pr_err("%s: failed to map %pOFn DIV6 clock register\n",
348 	of_property_read_string(np, "clock-output-names", &clk_name);
355 		pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
370 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);