Lines Matching refs:map
24 static int regcache_hw_init(struct regmap *map)
32 if (!map->num_reg_defaults_raw)
36 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
37 if (regmap_readable(map, i * map->reg_stride) &&
38 !regmap_volatile(map, i * map->reg_stride))
43 map->cache_bypass = true;
47 map->num_reg_defaults = count;
48 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
50 if (!map->reg_defaults)
53 if (!map->reg_defaults_raw) {
54 bool cache_bypass = map->cache_bypass;
55 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
58 map->cache_bypass = true;
59 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
64 ret = regmap_raw_read(map, 0, tmp_buf,
65 map->cache_size_raw);
66 map->cache_bypass = cache_bypass;
68 map->reg_defaults_raw = tmp_buf;
69 map->cache_free = true;
76 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
77 reg = i * map->reg_stride;
79 if (!regmap_readable(map, reg))
82 if (regmap_volatile(map, reg))
85 if (map->reg_defaults_raw) {
86 val = regcache_get_val(map, map->reg_defaults_raw, i);
88 bool cache_bypass = map->cache_bypass;
90 map->cache_bypass = true;
91 ret = regmap_read(map, reg, &val);
92 map->cache_bypass = cache_bypass;
94 dev_err(map->dev, "Failed to read %d: %d\n",
100 map->reg_defaults[j].reg = reg;
101 map->reg_defaults[j].def = val;
108 kfree(map->reg_defaults);
113 int regcache_init(struct regmap *map, const struct regmap_config *config)
119 if (map->cache_type == REGCACHE_NONE) {
121 dev_warn(map->dev,
124 map->cache_bypass = true;
129 dev_err(map->dev,
135 dev_err(map->dev,
141 if (config->reg_defaults[i].reg % map->reg_stride)
145 if (cache_types[i]->type == map->cache_type)
149 dev_err(map->dev, "Could not match cache type: %d\n",
150 map->cache_type);
154 map->num_reg_defaults = config->num_reg_defaults;
155 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156 map->reg_defaults_raw = config->reg_defaults_raw;
157 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
160 map->cache = NULL;
161 map->cache_ops = cache_types[i];
163 if (!map->cache_ops->read ||
164 !map->cache_ops->write ||
165 !map->cache_ops->name)
173 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
177 map->reg_defaults = tmp_buf;
178 } else if (map->num_reg_defaults_raw) {
183 ret = regcache_hw_init(map);
186 if (map->cache_bypass)
190 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
191 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
192 map->max_register_is_set = true;
195 if (map->cache_ops->init) {
196 dev_dbg(map->dev, "Initializing %s cache\n",
197 map->cache_ops->name);
198 ret = map->cache_ops->init(map);
205 kfree(map->reg_defaults);
206 if (map->cache_free)
207 kfree(map->reg_defaults_raw);
212 void regcache_exit(struct regmap *map)
214 if (map->cache_type == REGCACHE_NONE)
217 BUG_ON(!map->cache_ops);
219 kfree(map->reg_defaults);
220 if (map->cache_free)
221 kfree(map->reg_defaults_raw);
223 if (map->cache_ops->exit) {
224 dev_dbg(map->dev, "Destroying %s cache\n",
225 map->cache_ops->name);
226 map->cache_ops->exit(map);
233 * @map: map to configure.
239 int regcache_read(struct regmap *map,
244 if (map->cache_type == REGCACHE_NONE)
247 BUG_ON(!map->cache_ops);
249 if (!regmap_volatile(map, reg)) {
250 ret = map->cache_ops->read(map, reg, value);
253 trace_regmap_reg_read_cache(map, reg, *value);
264 * @map: map to configure.
270 int regcache_write(struct regmap *map,
273 if (map->cache_type == REGCACHE_NONE)
276 BUG_ON(!map->cache_ops);
278 if (!regmap_volatile(map, reg))
279 return map->cache_ops->write(map, reg, value);
284 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
289 if (!regmap_writeable(map, reg))
293 if (!map->no_sync_defaults)
297 ret = regcache_lookup_reg(map, reg);
298 if (ret >= 0 && val == map->reg_defaults[ret].def)
303 static int regcache_default_sync(struct regmap *map, unsigned int min,
308 for (reg = min; reg <= max; reg += map->reg_stride) {
312 if (regmap_volatile(map, reg) ||
313 !regmap_writeable(map, reg))
316 ret = regcache_read(map, reg, &val);
322 if (!regcache_reg_needs_sync(map, reg, val))
325 map->cache_bypass = true;
326 ret = _regmap_write(map, reg, val);
327 map->cache_bypass = false;
329 dev_err(map->dev, "Unable to sync register %#x. %d\n",
333 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
347 * @map: map to configure.
355 int regcache_sync(struct regmap *map)
363 if (WARN_ON(map->cache_type == REGCACHE_NONE))
366 BUG_ON(!map->cache_ops);
368 map->lock(map->lock_arg);
370 bypass = map->cache_bypass;
371 dev_dbg(map->dev, "Syncing %s cache\n",
372 map->cache_ops->name);
373 name = map->cache_ops->name;
374 trace_regcache_sync(map, name, "start");
376 if (!map->cache_dirty)
380 map->cache_bypass = true;
381 for (i = 0; i < map->patch_regs; i++) {
382 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
384 dev_err(map->dev, "Failed to write %x = %x: %d\n",
385 map->patch[i].reg, map->patch[i].def, ret);
389 map->cache_bypass = false;
391 if (map->cache_ops->sync)
392 ret = map->cache_ops->sync(map, 0, map->max_register);
394 ret = regcache_default_sync(map, 0, map->max_register);
397 map->cache_dirty = false;
401 map->cache_bypass = bypass;
402 map->no_sync_defaults = false;
410 rb_for_each(node, 0, &map->range_tree, rbtree_all) {
415 if (regcache_read(map, this->selector_reg, &i) != 0)
418 ret = _regmap_write(map, this->selector_reg, i);
420 dev_err(map->dev, "Failed to write %x = %x: %d\n",
426 map->unlock(map->lock_arg);
428 regmap_async_complete(map);
430 trace_regcache_sync(map, name, "stop");
439 * @map: map to sync.
448 int regcache_sync_region(struct regmap *map, unsigned int min,
455 if (WARN_ON(map->cache_type == REGCACHE_NONE))
458 BUG_ON(!map->cache_ops);
460 map->lock(map->lock_arg);
463 bypass = map->cache_bypass;
465 name = map->cache_ops->name;
466 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
468 trace_regcache_sync(map, name, "start region");
470 if (!map->cache_dirty)
473 map->async = true;
475 if (map->cache_ops->sync)
476 ret = map->cache_ops->sync(map, min, max);
478 ret = regcache_default_sync(map, min, max);
482 map->cache_bypass = bypass;
483 map->async = false;
484 map->no_sync_defaults = false;
485 map->unlock(map->lock_arg);
487 regmap_async_complete(map);
489 trace_regcache_sync(map, name, "stop region");
498 * @map: map to operate on
506 int regcache_drop_region(struct regmap *map, unsigned int min,
511 if (!map->cache_ops || !map->cache_ops->drop)
514 map->lock(map->lock_arg);
516 trace_regcache_drop_region(map, min, max);
518 ret = map->cache_ops->drop(map, min, max);
520 map->unlock(map->lock_arg);
527 * regcache_cache_only - Put a register map into cache only mode
529 * @map: map to configure
532 * When a register map is marked as cache only writes to the register
533 * map API will only update the register cache, they will not cause
538 void regcache_cache_only(struct regmap *map, bool enable)
540 map->lock(map->lock_arg);
541 WARN_ON(map->cache_type != REGCACHE_NONE &&
542 map->cache_bypass && enable);
543 map->cache_only = enable;
544 trace_regmap_cache_only(map, enable);
545 map->unlock(map->lock_arg);
552 * @map: map to mark
562 void regcache_mark_dirty(struct regmap *map)
564 map->lock(map->lock_arg);
565 map->cache_dirty = true;
566 map->no_sync_defaults = true;
567 map->unlock(map->lock_arg);
572 * regcache_cache_bypass - Put a register map into cache bypass mode
574 * @map: map to configure
577 * When a register map is marked with the cache bypass option, writes
578 * to the register map API will only update the hardware and not
582 void regcache_cache_bypass(struct regmap *map, bool enable)
584 map->lock(map->lock_arg);
585 WARN_ON(map->cache_only && enable);
586 map->cache_bypass = enable;
587 trace_regmap_cache_bypass(map, enable);
588 map->unlock(map->lock_arg);
595 * @map: map to check
600 bool regcache_reg_cached(struct regmap *map, unsigned int reg)
605 map->lock(map->lock_arg);
607 ret = regcache_read(map, reg, &val);
609 map->unlock(map->lock_arg);
615 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
619 if (map->format.format_val) {
620 map->format.format_val(base + (map->cache_word_size * idx),
625 switch (map->cache_word_size) {
649 unsigned int regcache_get_val(struct regmap *map, const void *base,
656 if (map->format.parse_val)
657 return map->format.parse_val(regcache_get_val_addr(map, base,
660 switch (map->cache_word_size) {
691 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
699 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
703 return r - map->reg_defaults;
716 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
720 if (!regcache_reg_needs_sync(map, reg, val))
723 map->cache_bypass = true;
725 ret = _regmap_write(map, reg, val);
727 map->cache_bypass = false;
730 dev_err(map->dev, "Unable to sync register %#x. %d\n",
734 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
740 static int regcache_sync_block_single(struct regmap *map, void *block,
749 regtmp = block_base + (i * map->reg_stride);
752 !regmap_writeable(map, regtmp))
755 val = regcache_get_val(map, block, i);
756 ret = regcache_sync_val(map, regtmp, val);
764 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
767 size_t val_bytes = map->format.val_bytes;
773 count = (cur - base) / map->reg_stride;
775 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
776 count * val_bytes, count, base, cur - map->reg_stride);
778 map->cache_bypass = true;
780 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
782 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
783 base, cur - map->reg_stride, ret);
785 map->cache_bypass = false;
792 static int regcache_sync_block_raw(struct regmap *map, void *block,
804 regtmp = block_base + (i * map->reg_stride);
807 !regmap_writeable(map, regtmp)) {
808 ret = regcache_sync_block_raw_flush(map, &data,
815 val = regcache_get_val(map, block, i);
816 if (!regcache_reg_needs_sync(map, regtmp, val)) {
817 ret = regcache_sync_block_raw_flush(map, &data,
825 data = regcache_get_val_addr(map, block, i);
830 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
831 map->reg_stride);
834 int regcache_sync_block(struct regmap *map, void *block,
839 if (regmap_can_raw_write(map) && !map->use_single_write)
840 return regcache_sync_block_raw(map, block, cache_present,
843 return regcache_sync_block_single(map, block, cache_present,