x86/events/core.c

194 	int i, num_counters = x86_pmu.num_counters;
197 		return num_counters;
200 		num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
202 	return num_counters;
207 	int i, num_counters = get_possible_num_counters();
209 	for (i = 0; i < num_counters; i++) {
214 	for (i = 0; i < num_counters; i++) {
225 	i = num_counters;
236 	int i, num_counters = get_possible_num_counters();
238 	for (i = 0; i < num_counters; i++) {
251 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
262 	for (i = 0; i < num_counters; i++) {
682 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
739 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
978 	int num_counters = hybrid(cpuc->pmu, num_counters);
1054 		int gpmax = num_counters;
1075 			gpmax = num_counters - cpuc->n_pair;
1160 	int num_counters = hybrid(cpuc->pmu, num_counters);
1165 	max_count = num_counters + num_counters_fixed;
1525 	int num_counters = hybrid(cpuc->pmu, num_counters);
1531 	if (!num_counters)
1558 	for (idx = 0; idx < num_counters; idx++) {
1685 	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2041 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2046 	pr_info("... generic registers:      %d\n",     num_counters);
2089 	if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2100 		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2106 		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2107 				   0, x86_pmu.num_counters, 0, 0);
2117 		x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2986 	cap->num_counters_gp	= x86_pmu.num_counters;