sparc/kernel/perf_event.c

827 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
845 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
864 				   struct hw_perf_event *hwc, int idx)
871 	prev_raw_count = local64_read(&hwc->prev_count);
874 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
882 	local64_sub(delta, &hwc->period_left);
888 				       struct hw_perf_event *hwc, int idx)
890 	s64 left = local64_read(&hwc->period_left);
891 	s64 period = hwc->sample_period;
895 	if (unlikely(period != hwc->last_period))
896 		left = period - (hwc->last_period - left);
900 		local64_set(&hwc->period_left, left);
901 		hwc->last_period = period;
907 		local64_set(&hwc->period_left, left);
908 		hwc->last_period = period;
914 	local64_set(&hwc->prev_count, (u64)-left);
957 		struct hw_perf_event *hwc = &cp->hw;
958 		int idx = hwc->idx;
964 		sparc_perf_event_set_period(cp, hwc, idx);
969 		if (hwc->state & PERF_HES_ARCH) {
973 			hwc->state = 0;
992 		struct hw_perf_event *hwc = &cp->hw;
993 		int idx = hwc->idx;
1153 	struct hw_perf_event *hwc = &event->hw;
1155 	sparc_perf_event_update(event, hwc, idx);
1419 	struct hw_perf_event *hwc = &event->hw;
1455 		hwc->event_base = perf_event_encode(pmap);
1461 		hwc->event_base = attr->config;
1465 	hwc->config_base = sparc_pmu->irq_bit;
1467 		hwc->config_base |= sparc_pmu->user_bit;
1469 		hwc->config_base |= sparc_pmu->priv_bit;
1471 		hwc->config_base |= sparc_pmu->hv_bit;
1481 	events[n] = hwc->event_base;
1490 	hwc->idx = PIC_NO_INDEX;
1498 	if (!hwc->sample_period) {
1499 		hwc->sample_period = MAX_PERIOD;
1500 		hwc->last_period = hwc->sample_period;
1501 		local64_set(&hwc->period_left, hwc->sample_period);
1655 		struct hw_perf_event *hwc;
1662 		hwc = &event->hw;
1663 		val = sparc_perf_event_update(event, hwc, idx);
1667 		perf_sample_data_init(&data, 0, hwc->last_period);
1668 		if (!sparc_perf_event_set_period(event, hwc, idx))