powerpc/kernel/eeh.c

176 			edev->pe->phb->global_number, edev->bdfn >> 8,
179 		edev->pe->phb->global_number, edev->bdfn >> 8,
269 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
274 	eeh_pe_for_each_dev(pe, edev, tmp)
283  * @pe: EEH PE
291 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
311 	if (!(pe->type & EEH_PE_PHB)) {
314 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
328 		eeh_ops->configure_bridge(pe);
329 		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
330 			eeh_pe_restore_bars(pe);
333 			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
337 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
357 static int eeh_phb_check_failure(struct eeh_pe *pe)
367 	phb_pe = eeh_phb_pe_get(pe->phb);
370 			__func__, pe->phb->global_number);
430 	struct eeh_pe *pe, *parent_pe;
444 	pe = eeh_dev_to_pe(edev);
447 	if (!pe) {
457 	ret = eeh_phb_check_failure(pe);
466 	if (eeh_pe_passed(pe))
477 	if (pe->state & EEH_PE_ISOLATED) {
478 		pe->check_count++;
479 		if (pe->check_count == EEH_MAX_FAILS) {
485 				pe->check_count,
502 	ret = eeh_ops->get_state(pe, NULL);
513 		pe->false_positives++;
523 	parent_pe = pe->parent;
532 			pe = parent_pe;
534 			       pe->phb->global_number, pe->addr,
535 			       pe->phb->global_number, parent_pe->addr);
548 	eeh_pe_mark_isolated(pe);
556 		__func__, pe->phb->global_number, pe->addr);
557 	eeh_send_failure_event(pe);
599  * @pe: EEH PE
606 int eeh_pci_enable(struct eeh_pe *pe, int function)
638 		rc = eeh_ops->get_state(pe, NULL);
653 	rc = eeh_ops->set_option(pe, function);
657 			__func__, function, pe->phb->global_number,
658 			pe->addr, rc);
662 		rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
729 	struct eeh_pe *pe = eeh_dev_to_pe(edev);
731 	if (!pe) {
739 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
740 		eeh_unfreeze_pe(pe);
741 		if (!(pe->type & EEH_PE_VF))
742 			eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
743 		eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
744 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
747 		eeh_pe_mark_isolated(pe);
748 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
749 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
750 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
751 		if (!(pe->type & EEH_PE_VF))
752 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
753 		eeh_ops->reset(pe, EEH_RESET_HOT);
756 		eeh_pe_mark_isolated(pe);
757 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
758 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
759 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
760 		if (!(pe->type & EEH_PE_VF))
761 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
762 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
765 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
794 	struct eeh_pe *pe;
797 	eeh_for_each_pe(root, pe) {
798 		if (eeh_pe_passed(pe)) {
799 			state = eeh_ops->get_state(pe, NULL);
803 					pe->phb->global_number, pe->addr);
804 				eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
812  * @pe: EEH PE
823 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
835 	eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
841 	eeh_pe_state_mark(pe, reset_state);
845 		ret = eeh_pe_reset(pe, type, include_passed);
847 			ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
852 				state, pe->phb->global_number, pe->addr, i + 1);
857 				pe->phb->global_number, pe->addr, i + 1);
860 		state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
863 				pe->phb->global_number, pe->addr);
871 				pe->phb->global_number, pe->addr, state, i + 1);
878 		eeh_pe_refreeze_passed(pe);
880 	eeh_pe_state_clear(pe, reset_state, true);
1069 	if (!edev || !edev->pdev || !edev->pe) {
1107 	if (!(edev->pe->state & EEH_PE_KEEP))
1113 int eeh_unfreeze_pe(struct eeh_pe *pe)
1117 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1120 			__func__, ret, pe->phb->global_number, pe->addr);
1124 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1127 			__func__, ret, pe->phb->global_number, pe->addr);
1142 static int eeh_pe_change_owner(struct eeh_pe *pe)
1150 	ret = eeh_ops->get_state(pe, NULL);
1159 	eeh_pe_for_each_dev(pe, edev, tmp) {
1178 			return eeh_pe_reset_and_recover(pe);
1182 	ret = eeh_unfreeze_pe(pe);
1184 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
1210 	if (!edev || !edev->pe)
1219 	ret = eeh_pe_change_owner(edev->pe);
1224 	atomic_inc(&edev->pe->pass_dev_cnt);
1254 	if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1258 	WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1259 	eeh_pe_change_owner(edev->pe);
1305 	if (!edev || !edev->pe)
1308 	return edev->pe;
1316  * @pe: EEH PE
1322 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1327 	if (!pe)
1338 			ret = eeh_pe_change_owner(pe);
1353 		ret = eeh_pci_enable(pe, option);
1367  * @pe: EEH PE
1372 int eeh_pe_get_state(struct eeh_pe *pe)
1378 	if (!pe)
1390 	if (pe->parent &&
1391 	    !(pe->state & EEH_PE_REMOVED) &&
1392 	    (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
1395 	result = eeh_ops->get_state(pe, NULL);
1415 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
1421 	eeh_pe_restore_bars(pe);
1427 	eeh_pe_for_each_dev(pe, edev, tmp) {
1441 	if (include_passed || !eeh_pe_passed(pe)) {
1442 		ret = eeh_unfreeze_pe(pe);
1445 			pe->phb->global_number, pe->addr);
1447 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
1454  * @pe: EEH PE
1462 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
1467 	if (!pe)
1475 		ret = eeh_ops->reset(pe, option);
1476 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
1480 		ret = eeh_pe_reenable_devices(pe, include_passed);
1489 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1491 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1492 		ret = eeh_ops->reset(pe, option);
1506  * @pe: EEH PE
1512 int eeh_pe_configure(struct eeh_pe *pe)
1517 	if (!pe)
1526  * @pe: the indicated PE
1536 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1540 	if (!pe)
1555 	return eeh_ops->err_inject(pe, type, func, addr, mask);
1646 	struct eeh_pe *pe;
1674 	pe = eeh_pe_get(hose, pe_no);
1675 	if (!pe)
1685 	__eeh_send_failure_event(pe);