include/asm/opal.h

30 int64_t opal_invalid_call(void);
31 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
33 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
35 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
37 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
40 int64_t opal_console_write(int64_t term_number, __be64 *length,
42 int64_t opal_console_read(int64_t term_number, __be64 *length,
44 int64_t opal_console_write_buffer_space(int64_t term_number,
46 int64_t opal_console_flush(int64_t term_number);
47 int64_t opal_rtc_read(__be32 *year_month_day,
49 int64_t opal_rtc_write(uint32_t year_month_day,
51 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
52 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
54 int64_t opal_cec_power_down(uint64_t request);
55 int64_t opal_cec_reboot(void);
56 int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
57 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
58 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
59 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
60 int64_t opal_poll_events(__be64 *outstanding_event_mask);
61 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
63 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
65 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
67 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
69 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
71 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
73 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
75 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
77 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
78 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
79 int64_t opal_register_exception_handler(uint64_t opal_exception,
82 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
86 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
88 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
90 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
92 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
96 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
98 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
103 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
106 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
110 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
113 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
115 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
117 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
119 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
120 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
122 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
124 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
127 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
130 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
131 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
132 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
133 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
136 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
139 int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
141 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
143 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
145 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
147 int64_t opal_pci_fence_phb(uint64_t phb_id);
148 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
149 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
150 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
151 int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
152 int64_t opal_get_dpo_status(__be64 *dpo_timeout);
153 int64_t opal_set_system_attention_led(uint8_t led_action);
154 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
156 int64_t opal_pci_poll(uint64_t id);
157 int64_t opal_return_cpu(void);
158 int64_t opal_check_token(uint64_t token);
159 int64_t opal_reinit_cpus(uint64_t flags);
161 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
162 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
164 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
166 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
169 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
170 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
171 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
172 int64_t opal_send_ack_elog(uint64_t log_id);
175 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
176 int64_t opal_manage_flash(uint8_t op);
177 int64_t opal_update_flash(uint64_t blk_list);
178 int64_t opal_dump_init(uint8_t dump_type);
179 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
180 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
181 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
182 int64_t opal_dump_ack(uint32_t dump_id);
183 int64_t opal_dump_resend_notification(void);
185 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
186 int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
188 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
189 int64_t opal_sync_host_reboot(void);
190 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
192 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
194 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
195 int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
196 int64_t opal_handle_hmi(void);
197 int64_t opal_handle_hmi2(__be64 *out_flags);
198 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
199 int64_t opal_unregister_dump_region(uint32_t id);
200 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
201 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
202 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
203 int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
204 int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
205 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
207 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
209 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
211 int64_t opal_prd_msg(struct opal_prd_msg *msg);
212 int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
214 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
217 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
219 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
221 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
223 int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
224 int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
225 int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
226 int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
228 int64_t opal_pci_poll2(uint64_t id, uint64_t data);
230 int64_t opal_int_get_xirr(__be32 *out_xirr, bool just_poll);
231 int64_t opal_int_set_cppr(uint8_t cppr);
232 int64_t opal_int_eoi(uint32_t xirr);
233 int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
234 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
237 int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
238 int64_t opal_xive_reset(uint64_t version);
239 int64_t opal_xive_get_irq_info(uint32_t girq,
245 int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
247 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
249 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
255 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
259 int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
260 int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
261 int64_t opal_xive_free_vp_block(uint64_t vp);
262 int64_t opal_xive_get_vp_info(uint64_t vp,
267 int64_t opal_xive_set_vp_info(uint64_t vp,
270 int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
271 int64_t opal_xive_free_irq(uint32_t girq);
272 int64_t opal_xive_sync(uint32_t type, uint32_t id);
273 int64_t opal_xive_dump(uint32_t type, uint32_t id);
274 int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
277 int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
280 int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
282 int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
284 int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
285 int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);