include/asm/cpm1.h

28 #define CPM_CR_RST	((ushort)0x8000)
29 #define CPM_CR_OPCODE	((ushort)0x0f00)
30 #define CPM_CR_CHAN	((ushort)0x00f0)
31 #define CPM_CR_FLG	((ushort)0x0001)
35 #define CPM_CR_CH_SCC1		((ushort)0x0000)
36 #define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */
37 #define CPM_CR_CH_SCC2		((ushort)0x0004)
38 #define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */
40 #define CPM_CR_CH_SCC3		((ushort)0x0008)
41 #define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */
42 #define CPM_CR_CH_SCC4		((ushort)0x000c)
43 #define CPM_CR_CH_SMC2		((ushort)0x000d)	/* SMC2 / DSP2 */
74 	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
75 	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
78 	ushort	smc_mrblr;	/* Max receive buffer length */
81 	ushort	smc_rbptr;	/* Internal */
82 	ushort	smc_ibc;	/* Internal */
86 	ushort	smc_tbptr;	/* Internal */
87 	ushort	smc_tbc;	/* Internal */
89 	ushort	smc_maxidl;	/* Maximum idle characters */
90 	ushort	smc_tmpidl;	/* Temporary idle counter */
91 	ushort	smc_brklen;	/* Last received break length */
92 	ushort	smc_brkec;	/* rcv'd break condition counter */
93 	ushort	smc_brkcr;	/* xmt break count register */
94 	ushort	smc_rmask;	/* Temporary bit mask */
96 	ushort	smc_rpbase;	/* Relocation pointer */
105 #define	SMCMR_REN	((ushort)0x0001)
106 #define SMCMR_TEN	((ushort)0x0002)
107 #define SMCMR_DM	((ushort)0x000c)
108 #define SMCMR_SM_GCI	((ushort)0x0000)
109 #define SMCMR_SM_UART	((ushort)0x0020)
110 #define SMCMR_SM_TRANS	((ushort)0x0030)
111 #define SMCMR_SM_MASK	((ushort)0x0030)
112 #define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
114 #define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
116 #define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
117 #define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
126 	ushort	scent_rbase;
127 	ushort	scent_tbase;
130 	ushort	scent_mrblr;
133 	ushort	scent_rbptr;
134 	ushort	scent_r_cnt;
138 	ushort	scent_tbptr;
139 	ushort	scent_t_cnt;
141 	ushort	scent_max_sl;
142 	ushort	scent_sl_cnt;
143 	ushort	scent_character1;
144 	ushort	scent_character2;
145 	ushort	scent_character3;
146 	ushort	scent_character4;
147 	ushort	scent_character5;
148 	ushort	scent_character6;
149 	ushort	scent_character7;
150 	ushort	scent_character8;
151 	ushort	scent_rccm;
152 	ushort	scent_rccr;
275 #define SCC_TODR_TOD		((ushort)0x8000)
285 	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
286 	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
289 	ushort	scc_mrblr;	/* Max receive buffer length */
292 	ushort	scc_rbptr;	/* Internal */
293 	ushort	scc_ibc;	/* Internal */
297 	ushort	scc_tbptr;	/* Internal */
298 	ushort	scc_tbc;	/* Internal */
317 	ushort	sen_pads;	/* Tx short frame pad character */
318 	ushort	sen_retlim;	/* Retry limit threshold */
319 	ushort	sen_retcnt;	/* Retry limit counter */
320 	ushort	sen_maxflr;	/* maximum frame length register */
321 	ushort	sen_minflr;	/* minimum frame length register */
322 	ushort	sen_maxd1;	/* maximum DMA1 length */
323 	ushort	sen_maxd2;	/* maximum DMA2 length */
324 	ushort	sen_maxd;	/* Rx max DMA */
325 	ushort	sen_dmacnt;	/* Rx DMA counter */
326 	ushort	sen_maxb;	/* Max BD byte count */
327 	ushort	sen_gaddr1;	/* Group address filter */
328 	ushort	sen_gaddr2;
329 	ushort	sen_gaddr3;
330 	ushort	sen_gaddr4;
335 	ushort	sen_tbuf0bcnt;	/* Internal */
336 	ushort	sen_paddrh;	/* physical address (MSB) */
337 	ushort	sen_paddrm;
338 	ushort	sen_paddrl;	/* physical address (LSB) */
339 	ushort	sen_pper;	/* persistence */
340 	ushort	sen_rfbdptr;	/* Rx first BD pointer */
341 	ushort	sen_tfbdptr;	/* Tx first BD pointer */
342 	ushort	sen_tlbdptr;	/* Tx last BD pointer */
347 	ushort	sen_tbuf1bcnt;	/* Internal */
348 	ushort	sen_txlen;	/* Tx Frame length counter */
349 	ushort	sen_iaddr1;	/* Individual address filter */
350 	ushort	sen_iaddr2;
351 	ushort	sen_iaddr3;
352 	ushort	sen_iaddr4;
353 	ushort	sen_boffcnt;	/* Backoff counter */
358 	ushort	sen_taddrh;	/* temp address (MSB) */
359 	ushort	sen_taddrm;
360 	ushort	sen_taddrl;	/* temp address (LSB) */
365 #define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
366 #define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
367 #define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
368 #define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
369 #define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
370 #define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
374 #define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
375 #define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
376 #define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
377 #define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
378 #define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
379 #define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
380 #define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
381 #define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
382 #define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
383 #define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
384 #define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
385 #define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
386 #define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
393 	ushort	scc_maxidl;	/* Maximum idle chars */
394 	ushort	scc_idlc;	/* temp idle counter */
395 	ushort	scc_brkcr;	/* Break count register */
396 	ushort	scc_parec;	/* receive parity error counter */
397 	ushort	scc_frmec;	/* receive framing error counter */
398 	ushort	scc_nosec;	/* receive noise counter */
399 	ushort	scc_brkec;	/* receive break condition counter */
400 	ushort	scc_brkln;	/* last received break length */
401 	ushort	scc_uaddr1;	/* UART address character 1 */
402 	ushort	scc_uaddr2;	/* UART address character 2 */
403 	ushort	scc_rtemp;	/* Temp storage */
404 	ushort	scc_toseq;	/* Transmit out of sequence char */
405 	ushort	scc_char1;	/* control character 1 */
406 	ushort	scc_char2;	/* control character 2 */
407 	ushort	scc_char3;	/* control character 3 */
408 	ushort	scc_char4;	/* control character 4 */
409 	ushort	scc_char5;	/* control character 5 */
410 	ushort	scc_char6;	/* control character 6 */
411 	ushort	scc_char7;	/* control character 7 */
412 	ushort	scc_char8;	/* control character 8 */
413 	ushort	scc_rccm;	/* receive control character mask */
414 	ushort	scc_rccr;	/* receive control character register */
415 	ushort	scc_rlbc;	/* receive last break character */
420 #define UART_SCCM_GLR		((ushort)0x1000)
421 #define UART_SCCM_GLT		((ushort)0x0800)
422 #define UART_SCCM_AB		((ushort)0x0200)
423 #define UART_SCCM_IDL		((ushort)0x0100)
424 #define UART_SCCM_GRA		((ushort)0x0080)
425 #define UART_SCCM_BRKE		((ushort)0x0040)
426 #define UART_SCCM_BRKS		((ushort)0x0020)
427 #define UART_SCCM_CCR		((ushort)0x0008)
428 #define UART_SCCM_BSY		((ushort)0x0004)
429 #define UART_SCCM_TX		((ushort)0x0002)
430 #define UART_SCCM_RX		((ushort)0x0001)
434 #define SCU_PSMR_FLC		((ushort)0x8000)
435 #define SCU_PSMR_SL		((ushort)0x4000)
436 #define SCU_PSMR_CL		((ushort)0x3000)
437 #define SCU_PSMR_UM		((ushort)0x0c00)
438 #define SCU_PSMR_FRZ		((ushort)0x0200)
439 #define SCU_PSMR_RZS		((ushort)0x0100)
440 #define SCU_PSMR_SYN		((ushort)0x0080)
441 #define SCU_PSMR_DRT		((ushort)0x0040)
442 #define SCU_PSMR_PEN		((ushort)0x0010)
443 #define SCU_PSMR_RPM		((ushort)0x000c)
444 #define SCU_PSMR_REVP		((ushort)0x0008)
445 #define SCU_PSMR_TPM		((ushort)0x0003)
446 #define SCU_PSMR_TEVP		((ushort)0x0002)
459 	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
460 	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
463 	ushort	iic_mrblr;	/* Max receive buffer length */
466 	ushort	iic_rbptr;	/* Internal */
467 	ushort	iic_rbc;	/* Internal */
471 	ushort	iic_tbptr;	/* Internal */
472 	ushort	iic_tbc;	/* Internal */
475 	ushort	iic_rpbase;	/* Relocation pointer */
513 #define	CPMVEC_PIO_PC15		((ushort)0x1f)
514 #define	CPMVEC_SCC1		((ushort)0x1e)
515 #define	CPMVEC_SCC2		((ushort)0x1d)
516 #define	CPMVEC_SCC3		((ushort)0x1c)
517 #define	CPMVEC_SCC4		((ushort)0x1b)
518 #define	CPMVEC_PIO_PC14		((ushort)0x1a)
519 #define	CPMVEC_TIMER1		((ushort)0x19)
520 #define	CPMVEC_PIO_PC13		((ushort)0x18)
521 #define	CPMVEC_PIO_PC12		((ushort)0x17)
522 #define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
523 #define CPMVEC_IDMA1		((ushort)0x15)
524 #define CPMVEC_IDMA2		((ushort)0x14)
525 #define CPMVEC_TIMER2		((ushort)0x12)
526 #define CPMVEC_RISCTIMER	((ushort)0x11)
527 #define CPMVEC_I2C		((ushort)0x10)
528 #define	CPMVEC_PIO_PC11		((ushort)0x0f)
529 #define	CPMVEC_PIO_PC10		((ushort)0x0e)
530 #define CPMVEC_TIMER3		((ushort)0x0c)
531 #define	CPMVEC_PIO_PC9		((ushort)0x0b)
532 #define	CPMVEC_PIO_PC8		((ushort)0x0a)
533 #define	CPMVEC_PIO_PC7		((ushort)0x09)
534 #define CPMVEC_TIMER4		((ushort)0x07)
535 #define	CPMVEC_PIO_PC6		((ushort)0x06)
536 #define	CPMVEC_SPI		((ushort)0x05)
537 #define	CPMVEC_SMC1		((ushort)0x04)
538 #define	CPMVEC_SMC2		((ushort)0x03)
539 #define	CPMVEC_PIO_PC5		((ushort)0x02)
540 #define	CPMVEC_PIO_PC4		((ushort)0x01)
541 #define	CPMVEC_ERROR		((ushort)0x00)