Lines Matching refs:Mask
255 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
258 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
314 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
332 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */
348 #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
349 #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
363 /* Bit 10.. 0: Mask for Gate Clock */
399 #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
412 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
413 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
437 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
439 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
479 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
480 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
629 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
734 #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
735 #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
736 #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
737 #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
746 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
820 /* B0_IMSK 32 bit Interrupt Mask Register */
822 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
827 #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
849 #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */
851 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */
861 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
862 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
944 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */
1275 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
1355 #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
1378 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1379 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1382 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1384 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1419 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1422 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1430 #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
1445 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1501 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1503 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1506 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
1508 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1573 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
1574 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
1576 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
1586 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
1587 #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
1588 #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
1623 #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
1630 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1631 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1632 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1633 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1641 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
1642 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1643 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1644 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1645 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1646 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1693 /* Interrupt Mask Registers */
1694 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1695 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1696 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1850 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
1851 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
1864 #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
1865 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
1866 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
1867 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
1937 /* Rx GMAC FIFO Flush Mask (default) */
2107 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */