dev/igc/igc_phy.c

22 	struct igc_phy_info *phy = &hw->phy;
26 	phy->ops.init_params = igc_null_ops_generic;
27 	phy->ops.acquire = igc_null_ops_generic;
28 	phy->ops.check_reset_block = igc_null_ops_generic;
29 	phy->ops.force_speed_duplex = igc_null_ops_generic;
30 	phy->ops.get_info = igc_null_ops_generic;
31 	phy->ops.set_page = igc_null_set_page;
32 	phy->ops.read_reg = igc_null_read_reg;
33 	phy->ops.read_reg_locked = igc_null_read_reg;
34 	phy->ops.read_reg_page = igc_null_read_reg;
35 	phy->ops.release = igc_null_phy_generic;
36 	phy->ops.reset = igc_null_ops_generic;
37 	phy->ops.set_d0_lplu_state = igc_null_lplu_state;
38 	phy->ops.set_d3_lplu_state = igc_null_lplu_state;
39 	phy->ops.write_reg = igc_null_write_reg;
40 	phy->ops.write_reg_locked = igc_null_write_reg;
41 	phy->ops.write_reg_page = igc_null_write_reg;
42 	phy->ops.power_up = igc_null_phy_generic;
43 	phy->ops.power_down = igc_null_phy_generic;
135 	struct igc_phy_info *phy = &hw->phy;
141 	if (!phy->ops.read_reg)
144 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
148 	phy->id = (u32)(phy_id << 16);
150 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
154 	phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
155 	phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
171 	struct igc_phy_info *phy = &hw->phy;
186 		(phy->addr << IGC_MDIC_PHY_SHIFT) |
230 	struct igc_phy_info *phy = &hw->phy;
246 		(phy->addr << IGC_MDIC_PHY_SHIFT) |
290 	struct igc_phy_info *phy = &hw->phy;
298 	phy->autoneg_advertised &= phy->autoneg_mask;
301 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
305 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
307 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
313 	if (phy->autoneg_mask & ADVERTISE_2500_FULL) {
315 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
341 	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
344 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
350 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
356 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
362 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
368 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
372 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
378 	if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
382 	if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
443 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
449 	if (phy->autoneg_mask & ADVERTISE_1000_FULL)
450 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
453 	if (phy->autoneg_mask & ADVERTISE_2500_FULL)
454 		ret_val = phy->ops.write_reg(hw,
474 	struct igc_phy_info *phy = &hw->phy;
483 	phy->autoneg_advertised &= phy->autoneg_mask;
488 	if (!phy->autoneg_advertised)
489 		phy->autoneg_advertised = phy->autoneg_mask;
502 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
507 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
514 	if (phy->autoneg_wait_to_complete) {
555 		ret_val = hw->phy.ops.force_speed_duplex(hw);
611 	/* Disable autoneg on the phy */
658 	struct igc_phy_info *phy = &hw->phy;
664 	if (!hw->phy.ops.read_reg)
667 	ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
673 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
682 		if (phy->smart_speed == igc_smart_speed_on) {
683 			ret_val = phy->ops.read_reg(hw,
690 			ret_val = phy->ops.write_reg(hw,
695 		} else if (phy->smart_speed == igc_smart_speed_off) {
696 			ret_val = phy->ops.read_reg(hw,
703 			ret_val = phy->ops.write_reg(hw,
709 	} else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
710 		   (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
711 		   (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
713 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
719 		ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
725 		ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
742 	struct igc_phy_info *phy = &hw->phy;
747 	switch (phy->type) {
751 		phy->speed_downgraded = false;
772 	if (!hw->phy.ops.read_reg)
777 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
780 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
811 	if (!hw->phy.ops.read_reg)
819 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
830 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
857 	struct igc_phy_info *phy = &hw->phy;
863 	if (phy->ops.check_reset_block) {
864 		ret_val = phy->ops.check_reset_block(hw);
869 	ret_val = phy->ops.acquire(hw);
879 	usec_delay(phy->reset_delay_us);
893 		DEBUGOUT("Timeout expired after a phy reset\n");
895 	phy->ops.release(hw);
913 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
915 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
932 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
934 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
956 		ret_val = hw->phy.ops.acquire(hw);
962 		hw->phy.ops.release(hw);
990 		ret_val = hw->phy.ops.acquire(hw);
996 		hw->phy.ops.release(hw);
1020 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1024 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1028 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1034 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1036 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1041 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);