dev/igc/igc_phy.c

136 	s32 ret_val = IGC_SUCCESS;
144 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
145 	if (ret_val)
146 		return ret_val;
150 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
151 	if (ret_val)
152 		return ret_val;
291 	s32 ret_val;
301 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
302 	if (ret_val)
303 		return ret_val;
307 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
309 		if (ret_val)
310 			return ret_val;
315 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
320 		if (ret_val)
321 			return ret_val;
443 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
444 	if (ret_val)
445 		return ret_val;
450 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
454 		ret_val = phy->ops.write_reg(hw,
460 	return ret_val;
475 	s32 ret_val;
492 	ret_val = igc_phy_setup_autoneg(hw);
493 	if (ret_val) {
495 		return ret_val;
502 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
503 	if (ret_val)
504 		return ret_val;
507 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
508 	if (ret_val)
509 		return ret_val;
515 		ret_val = igc_wait_autoneg(hw);
516 		if (ret_val) {
518 			return ret_val;
524 	return ret_val;
538 	s32 ret_val;
547 		ret_val = igc_copper_link_autoneg(hw);
548 		if (ret_val)
549 			return ret_val;
555 		ret_val = hw->phy.ops.force_speed_duplex(hw);
556 		if (ret_val) {
558 			return ret_val;
565 	ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
567 	if (ret_val)
568 		return ret_val;
573 		ret_val = igc_config_fc_after_link_up_generic(hw);
578 	return ret_val;
659 	s32 ret_val;
667 	ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
668 	if (ret_val)
669 		return ret_val;
673 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
675 		if (ret_val)
676 			return ret_val;
683 			ret_val = phy->ops.read_reg(hw,
686 			if (ret_val)
687 				return ret_val;
690 			ret_val = phy->ops.write_reg(hw,
693 			if (ret_val)
694 				return ret_val;
696 			ret_val = phy->ops.read_reg(hw,
699 			if (ret_val)
700 				return ret_val;
703 			ret_val = phy->ops.write_reg(hw,
706 			if (ret_val)
707 				return ret_val;
713 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
715 		if (ret_val)
716 			return ret_val;
719 		ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
721 		if (ret_val)
722 			return ret_val;
725 		ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
729 	return ret_val;
743 	s32 ret_val;
755 	return ret_val;
767 	s32 ret_val = IGC_SUCCESS;
777 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
778 		if (ret_val)
780 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
781 		if (ret_val)
791 	return ret_val;
806 	s32 ret_val = IGC_SUCCESS;
819 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
820 		if (ret_val) {
830 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
831 		if (ret_val)
843 	return ret_val;
858 	s32 ret_val;
864 		ret_val = phy->ops.check_reset_block(hw);
865 		if (ret_val)
869 	ret_val = phy->ops.acquire(hw);
870 	if (ret_val)
871 		return ret_val;
897 	return ret_val;
948 	s32 ret_val;
956 		ret_val = hw->phy.ops.acquire(hw);
957 		if (ret_val)
958 			return ret_val;
959 		ret_val = igc_write_phy_reg_mdic(hw, offset, data);
960 		if (ret_val)
961 			return ret_val;
964 		ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
967 	return ret_val;
982 	s32 ret_val;
990 		ret_val = hw->phy.ops.acquire(hw);
991 		if (ret_val)
992 			return ret_val;
993 		ret_val = igc_read_phy_reg_mdic(hw, offset, data);
994 		if (ret_val)
995 			return ret_val;
998 		ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
1001 	return ret_val;
1016 	s32 ret_val;
1020 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1021 	if (ret_val)
1022 		return ret_val;
1024 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1025 	if (ret_val)
1026 		return ret_val;
1028 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1030 	if (ret_val)
1031 		return ret_val;
1034 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1036 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1037 	if (ret_val)
1038 		return ret_val;
1041 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
1042 	if (ret_val)
1043 		return ret_val;
1045 	return ret_val;