dev/ale/if_ale.c

206 ale_miibus_readreg(device_t dev, int phy, int reg)
215 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
224 		device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
232 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
242 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
251 		device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
262 	uint32_t reg;
295 		reg = CSR_READ_4(sc, ALE_MAC_CFG);
296 		reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
297 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
365 	uint32_t ea[2], reg;
368 	reg = CSR_READ_4(sc, ALE_SPI_CTRL);
369 	if ((reg & SPI_VPD_ENB) != 0) {
370 		reg &= ~SPI_VPD_ENB;
371 		CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
383 			reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
384 			if ((reg & TWSI_CTRL_SW_LD_START) == 0)
1499 	uint32_t reg, pmcs;
1508 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1509 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1510 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1530 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1531 	reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1534 		reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1536 		reg |= MAC_CFG_RX_ENB;
1537 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1541 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1542 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1543 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
2084 	uint32_t reg;
2089 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2090 	reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2096 		reg |= MAC_CFG_SPEED_10_100;
2099 		reg |= MAC_CFG_SPEED_1000;
2103 		reg |= MAC_CFG_FULL_DUPLEX;
2105 			reg |= MAC_CFG_TX_FC;
2107 			reg |= MAC_CFG_RX_FC;
2109 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2116 	uint32_t *reg;
2119 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2124 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2136 	uint32_t *reg;
2146 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2147 		*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2151 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2152 		*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2598 	uint32_t reg;
2614 		if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2620 		device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2641 	uint32_t reg, rxf_hi, rxf_lo;
2720 	reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2721 	reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2722 	CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2723 	reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2724 	reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2725 	reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2727 		reg |= MASTER_IM_RX_TIMER_ENB;
2729 		reg |= MASTER_IM_TX_TIMER_ENB;
2730 	CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2761 			reg = sc->ale_max_frame_size;
2763 			reg = (sc->ale_max_frame_size * 2) / 3;
2765 			reg = sc->ale_max_frame_size / 2;
2767 		    roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2771 	reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2773 	reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2775 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2779 		reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2781 		    (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2785 		reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2786 		rxf_hi = (reg * 7) / 10;
2787 		rxf_lo = (reg * 3)/ 10;
2804 	reg = 0;
2806 		reg |= DMA_CFG_TXCMB_ENB;
2809 	    sc->ale_dma_rd_burst | reg |
2837 	reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2841 		reg |= MAC_CFG_SPEED_10_100;
2843 		reg |= MAC_CFG_SPEED_1000;
2844 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2870 	uint32_t reg;
2887 	reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2888 	reg &= ~TXQ_CFG_ENB;
2889 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2890 	reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2891 	reg &= ~RXQ_CFG_ENB;
2892 	CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2893 	reg = CSR_READ_4(sc, ALE_DMA_CFG);
2894 	reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2895 	CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2921 	uint32_t reg;
2926 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2927 	if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2928 		reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2929 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2933 		reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2934 		if (reg == 0)
2940 		    "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2999 	uint32_t reg;
3004 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
3005 	reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3007 		reg |= MAC_CFG_VLAN_TAG_STRIP;
3008 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);