Lines Matching refs:sc
278 static void xl_choose_media(struct xl_softc *sc, int *media);
358 xl_wait(struct xl_softc *sc)
363 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
367 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
368 device_printf(sc->xl_dev, "command never completed!\n");
387 struct xl_softc *sc;
390 sc = device_get_softc(dev);
393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
394 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
406 struct xl_softc *sc;
408 sc = device_get_softc(dev);
411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
412 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
419 struct xl_softc *sc;
421 sc = device_get_softc(dev);
432 struct xl_softc *sc;
434 sc = device_get_softc(dev);
447 struct xl_softc *sc;
451 sc = device_get_softc(dev);
452 mii = device_get_softc(sc->xl_miibus);
454 xl_setcfg(sc);
458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
461 if (sc->xl_type == XL_TYPE_905B) {
470 if (sc->xl_type == XL_TYPE_905B)
473 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
489 struct xl_softc *sc;
493 sc = device_get_softc(dev);
494 mii = device_get_softc(sc->xl_miibus);
497 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
501 if (sc->xl_type == XL_TYPE_905B &&
502 sc->xl_media == XL_MEDIAOPT_10FL) {
504 device_printf(sc->xl_dev, "found 10baseFL\n");
508 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
513 device_printf(sc->xl_dev, "found AUI\n");
518 if (sc->xl_media & XL_MEDIAOPT_BNC) {
520 device_printf(sc->xl_dev, "found BNC\n");
530 xl_eeprom_wait(struct xl_softc *sc)
535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
542 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
554 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
568 if (xl_eeprom_wait(sc))
571 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
575 if (sc->xl_flags & XL_FLAG_8BITROM)
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
579 CSR_WRITE_2(sc, XL_W0_EE_CMD,
581 err = xl_eeprom_wait(sc);
584 word = CSR_READ_2(sc, XL_W0_EE_DATA);
596 xl_rxfilter(struct xl_softc *sc)
599 if (sc->xl_type == XL_TYPE_905B)
600 xl_rxfilter_90xB(sc);
602 xl_rxfilter_90x(sc);
610 xl_rxfilter_90x(struct xl_softc *sc)
616 XL_LOCK_ASSERT(sc);
618 ifp = sc->xl_ifp;
621 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
656 xl_rxfilter_90xB(struct xl_softc *sc)
664 XL_LOCK_ASSERT(sc);
666 ifp = sc->xl_ifp;
669 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
711 CSR_WRITE_2(sc, XL_COMMAND,
720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
725 xl_setcfg(struct xl_softc *sc)
729 /*XL_LOCK_ASSERT(sc);*/
732 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
734 if (sc->xl_media & XL_MEDIAOPT_MII ||
735 sc->xl_media & XL_MEDIAOPT_BT4)
737 if (sc->xl_media & XL_MEDIAOPT_BTX)
740 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
745 xl_setmode(struct xl_softc *sc, int media)
751 XL_LOCK_ASSERT(sc);
754 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
756 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
758 if (sc->xl_media & XL_MEDIAOPT_BT) {
761 sc->xl_xcvr = XL_XCVR_10BT;
770 if (sc->xl_media & XL_MEDIAOPT_BFX) {
773 sc->xl_xcvr = XL_XCVR_100BFX;
781 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
784 sc->xl_xcvr = XL_XCVR_AUI;
793 sc->xl_xcvr = XL_XCVR_AUI;
802 if (sc->xl_media & XL_MEDIAOPT_BNC) {
805 sc->xl_xcvr = XL_XCVR_COAX;
817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
821 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
822 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
830 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
832 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
837 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
841 xl_reset(struct xl_softc *sc)
845 XL_LOCK_ASSERT(sc);
848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
849 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
859 if (sc->xl_flags & XL_FLAG_USE_MMIO)
864 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
869 device_printf(sc->xl_dev, "reset didn't complete\n");
878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
880 xl_wait(sc);
881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
882 xl_wait(sc);
884 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
885 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
887 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
888 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
889 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
891 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
935 xl_mediacheck(struct xl_softc *sc)
944 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
949 if (sc->xl_xcvr <= XL_XCVR_AUTO)
952 device_printf(sc->xl_dev,
953 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
954 device_printf(sc->xl_dev,
958 if (sc->xl_type == XL_TYPE_905B &&
959 sc->xl_media & XL_MEDIAOPT_10FL)
961 device_printf(sc->xl_dev,
963 device_printf(sc->xl_dev,
965 device_printf(sc->xl_dev,
969 xl_choose_xcvr(sc, 1);
973 xl_choose_xcvr(struct xl_softc *sc, int verbose)
982 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
987 sc->xl_media = XL_MEDIAOPT_BT;
988 sc->xl_xcvr = XL_XCVR_10BT;
990 device_printf(sc->xl_dev,
995 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
996 sc->xl_xcvr = XL_XCVR_10BT;
998 device_printf(sc->xl_dev,
1002 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1003 sc->xl_xcvr = XL_XCVR_10BT;
1005 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1008 sc->xl_media = XL_MEDIAOPT_10FL;
1009 sc->xl_xcvr = XL_XCVR_AUI;
1011 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1025 sc->xl_media = XL_MEDIAOPT_MII;
1026 sc->xl_xcvr = XL_XCVR_MII;
1028 device_printf(sc->xl_dev, "guessing MII\n");
1032 sc->xl_media = XL_MEDIAOPT_BT4;
1033 sc->xl_xcvr = XL_XCVR_MII;
1035 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1043 sc->xl_media = XL_MEDIAOPT_BTX;
1044 sc->xl_xcvr = XL_XCVR_AUTO;
1046 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1049 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1050 sc->xl_xcvr = XL_XCVR_AUTO;
1052 device_printf(sc->xl_dev,
1056 device_printf(sc->xl_dev,
1058 sc->xl_media = XL_MEDIAOPT_BT;
1072 struct xl_softc *sc;
1078 sc = device_get_softc(dev);
1079 sc->xl_dev = dev;
1083 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1085 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1089 sc->xl_flags = 0;
1091 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1094 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1099 sc->xl_flags |= XL_FLAG_8BITROM;
1101 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1107 sc->xl_flags |= XL_FLAG_FUNCREG;
1113 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1116 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1118 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1120 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1122 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1125 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1129 sc->xl_flags |= XL_FLAG_PHYOK;
1139 sc->xl_flags |= XL_FLAG_NO_MMIO;
1150 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1154 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1157 if (sc->xl_res != NULL) {
1158 sc->xl_flags |= XL_FLAG_USE_MMIO;
1164 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1165 if (sc->xl_res == NULL) {
1174 sc->xl_btag = rman_get_bustag(sc->xl_res);
1175 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1177 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1179 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1182 if (sc->xl_fres == NULL) {
1188 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1189 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1194 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1196 if (sc->xl_irq == NULL) {
1203 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1209 ifp->if_softc = sc;
1213 XL_LOCK(sc);
1214 xl_reset(sc);
1215 XL_UNLOCK(sc);
1220 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1226 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1227 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1239 &sc->xl_ldata.xl_rx_tag);
1245 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1246 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1247 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1250 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1251 sc->xl_ldata.xl_rx_tag = NULL;
1255 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1256 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1258 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1261 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1262 sc->xl_ldata.xl_rx_dmamap);
1263 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1264 sc->xl_ldata.xl_rx_tag = NULL;
1271 &sc->xl_ldata.xl_tx_tag);
1277 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1278 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1279 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1282 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1283 sc->xl_ldata.xl_tx_tag = NULL;
1287 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1288 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1290 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1293 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1294 sc->xl_ldata.xl_tx_dmamap);
1295 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1296 sc->xl_ldata.xl_tx_tag = NULL;
1306 NULL, &sc->xl_mtag);
1313 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1327 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1328 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1329 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1330 sc->xl_type = XL_TYPE_905B;
1332 sc->xl_type = XL_TYPE_90X;
1335 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1337 sc->xl_pmcap = pmcap;
1338 sc->xl_flags |= XL_FLAG_WOL;
1340 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1347 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1352 if (sc->xl_type == XL_TYPE_905B) {
1360 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1378 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1380 device_printf(dev, "media options word: %x\n", sc->xl_media);
1382 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1383 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1384 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1385 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1389 sc->xl_xcvr = XL_XCVR_10BT;
1392 xl_mediacheck(sc);
1394 if (sc->xl_media & XL_MEDIAOPT_MII ||
1395 sc->xl_media & XL_MEDIAOPT_BTX ||
1396 sc->xl_media & XL_MEDIAOPT_BT4) {
1399 xl_setcfg(sc);
1407 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1409 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1411 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1424 if (sc->xl_xcvr == XL_XCVR_AUTO)
1425 xl_choose_xcvr(sc, bootverbose);
1430 if (sc->xl_media & XL_MEDIAOPT_BT) {
1433 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1434 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1435 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1436 ifmedia_add(&sc->ifmedia,
1440 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1444 if (sc->xl_type == XL_TYPE_905B &&
1445 sc->xl_media == XL_MEDIAOPT_10FL) {
1448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1449 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1451 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1452 ifmedia_add(&sc->ifmedia,
1457 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1461 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1467 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1470 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1474 xl_choose_media(sc, &media);
1476 if (sc->xl_miibus == NULL)
1477 ifmedia_set(&sc->ifmedia, media);
1480 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1482 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1490 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1491 NULL, xl_intr, sc, &sc->xl_intrhand);
1512 xl_choose_media(struct xl_softc *sc, int *media)
1515 XL_LOCK(sc);
1517 switch (sc->xl_xcvr) {
1520 xl_setmode(sc, *media);
1523 if (sc->xl_type == XL_TYPE_905B &&
1524 sc->xl_media == XL_MEDIAOPT_10FL) {
1526 xl_setmode(sc, *media);
1529 xl_setmode(sc, *media);
1534 xl_setmode(sc, *media);
1545 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1546 sc->xl_xcvr);
1555 XL_UNLOCK(sc);
1568 struct xl_softc *sc;
1572 sc = device_get_softc(dev);
1573 ifp = sc->xl_ifp;
1575 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1582 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1592 XL_LOCK(sc);
1593 xl_stop(sc);
1594 XL_UNLOCK(sc);
1595 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1596 callout_drain(&sc->xl_tick_callout);
1599 if (sc->xl_miibus)
1600 device_delete_child(dev, sc->xl_miibus);
1602 ifmedia_removeall(&sc->ifmedia);
1604 if (sc->xl_intrhand)
1605 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1606 if (sc->xl_irq)
1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1608 if (sc->xl_fres != NULL)
1610 XL_PCI_FUNCMEM, sc->xl_fres);
1611 if (sc->xl_res)
1612 bus_release_resource(dev, res, rid, sc->xl_res);
1617 if (sc->xl_mtag) {
1618 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1619 bus_dma_tag_destroy(sc->xl_mtag);
1621 if (sc->xl_ldata.xl_rx_tag) {
1622 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1623 sc->xl_ldata.xl_rx_dmamap);
1624 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1625 sc->xl_ldata.xl_rx_dmamap);
1626 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1628 if (sc->xl_ldata.xl_tx_tag) {
1629 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1630 sc->xl_ldata.xl_tx_dmamap);
1631 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1632 sc->xl_ldata.xl_tx_dmamap);
1633 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1636 mtx_destroy(&sc->xl_mtx);
1645 xl_list_tx_init(struct xl_softc *sc)
1651 XL_LOCK_ASSERT(sc);
1653 cd = &sc->xl_cdata;
1654 ld = &sc->xl_ldata;
1657 error = bus_dmamap_create(sc->xl_mtag, 0,
1680 xl_list_tx_init_90xB(struct xl_softc *sc)
1686 XL_LOCK_ASSERT(sc);
1688 cd = &sc->xl_cdata;
1689 ld = &sc->xl_ldata;
1692 error = bus_dmamap_create(sc->xl_mtag, 0,
1727 xl_list_rx_init(struct xl_softc *sc)
1734 XL_LOCK_ASSERT(sc);
1736 cd = &sc->xl_cdata;
1737 ld = &sc->xl_ldata;
1741 error = bus_dmamap_create(sc->xl_mtag, 0,
1745 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1770 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1777 XL_LOCK_ASSERT(sc);
1788 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1792 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1799 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1801 c->xl_map = sc->xl_tmpmap;
1802 sc->xl_tmpmap = map;
1807 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1812 xl_rx_resync(struct xl_softc *sc)
1817 XL_LOCK_ASSERT(sc);
1819 pos = sc->xl_cdata.xl_rx_head;
1830 sc->xl_cdata.xl_rx_head = pos;
1840 xl_rxeof(struct xl_softc *sc)
1843 struct ifnet *ifp = sc->xl_ifp;
1849 XL_LOCK_ASSERT(sc);
1851 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1853 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1856 if (sc->rxcycles <= 0)
1858 sc->rxcycles--;
1861 cur_rx = sc->xl_cdata.xl_rx_head;
1862 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1884 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1885 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1895 device_printf(sc->xl_dev,
1899 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1900 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1905 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1916 if (xl_newbuf(sc, cur_rx)) {
1919 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1920 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1923 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1924 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1946 XL_UNLOCK(sc);
1948 XL_LOCK(sc);
1971 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1972 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1974 xl_wait(sc);
1975 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1976 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1989 struct xl_softc *sc = (struct xl_softc *)arg;
1991 XL_LOCK(sc);
1992 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1993 xl_rxeof(sc);
1994 XL_UNLOCK(sc);
2002 xl_txeof(struct xl_softc *sc)
2005 struct ifnet *ifp = sc->xl_ifp;
2007 XL_LOCK_ASSERT(sc);
2018 while (sc->xl_cdata.xl_tx_head != NULL) {
2019 cur_tx = sc->xl_cdata.xl_tx_head;
2021 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2024 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2025 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2027 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2033 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2034 sc->xl_cdata.xl_tx_free = cur_tx;
2037 if (sc->xl_cdata.xl_tx_head == NULL) {
2038 sc->xl_wdog_timer = 0;
2039 sc->xl_cdata.xl_tx_tail = NULL;
2041 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2042 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2043 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2044 sc->xl_cdata.xl_tx_head->xl_phys);
2045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2051 xl_txeof_90xB(struct xl_softc *sc)
2054 struct ifnet *ifp = sc->xl_ifp;
2057 XL_LOCK_ASSERT(sc);
2059 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2061 idx = sc->xl_cdata.xl_tx_cons;
2062 while (idx != sc->xl_cdata.xl_tx_prod) {
2063 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2070 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2072 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2079 sc->xl_cdata.xl_tx_cnt--;
2083 if (sc->xl_cdata.xl_tx_cnt == 0)
2084 sc->xl_wdog_timer = 0;
2085 sc->xl_cdata.xl_tx_cons = idx;
2097 xl_txeoc(struct xl_softc *sc)
2101 XL_LOCK_ASSERT(sc);
2103 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2107 device_printf(sc->xl_dev,
2109 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2110 xl_wait(sc);
2111 if (sc->xl_type == XL_TYPE_905B) {
2112 if (sc->xl_cdata.xl_tx_cnt) {
2116 i = sc->xl_cdata.xl_tx_cons;
2117 c = &sc->xl_cdata.xl_tx_chain[i];
2118 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2120 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2121 sc->xl_wdog_timer = 5;
2124 if (sc->xl_cdata.xl_tx_head != NULL) {
2125 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2126 sc->xl_cdata.xl_tx_head->xl_phys);
2127 sc->xl_wdog_timer = 5;
2134 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2136 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2137 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2138 device_printf(sc->xl_dev,
2139 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2141 CSR_WRITE_2(sc, XL_COMMAND,
2142 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2143 if (sc->xl_type == XL_TYPE_905B) {
2144 CSR_WRITE_2(sc, XL_COMMAND,
2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2157 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2164 struct xl_softc *sc = arg;
2165 struct ifnet *ifp = sc->xl_ifp;
2168 XL_LOCK(sc);
2172 XL_UNLOCK(sc);
2180 status = CSR_READ_2(sc, XL_STATUS);
2183 CSR_WRITE_2(sc, XL_COMMAND,
2186 status = atomic_get((int32 *)&sc->xl_intr_status);
2193 if (xl_rxeof(sc) == 0) {
2194 while (xl_rx_resync(sc))
2195 xl_rxeof(sc);
2200 if (sc->xl_type == XL_TYPE_905B)
2201 xl_txeof_90xB(sc);
2203 xl_txeof(sc);
2208 xl_txeoc(sc);
2213 xl_init_locked(sc);
2218 xl_stats_update(sc);
2220 status = CSR_READ_2(sc, XL_STATUS);
2223 CSR_WRITE_2(sc, XL_COMMAND,
2230 if (sc->xl_type == XL_TYPE_905B)
2236 XL_UNLOCK(sc);
2243 struct xl_softc *sc = ifp->if_softc;
2246 XL_LOCK(sc);
2249 XL_UNLOCK(sc);
2256 struct xl_softc *sc = ifp->if_softc;
2259 XL_LOCK_ASSERT(sc);
2261 sc->rxcycles = count;
2262 rx_npkts = xl_rxeof(sc);
2263 if (sc->xl_type == XL_TYPE_905B)
2264 xl_txeof_90xB(sc);
2266 xl_txeof(sc);
2269 if (sc->xl_type == XL_TYPE_905B)
2278 status = CSR_READ_2(sc, XL_STATUS);
2280 CSR_WRITE_2(sc, XL_COMMAND,
2285 xl_txeoc(sc);
2290 xl_init_locked(sc);
2294 xl_stats_update(sc);
2304 struct xl_softc *sc = xsc;
2307 XL_LOCK_ASSERT(sc);
2309 if (sc->xl_miibus != NULL) {
2310 mii = device_get_softc(sc->xl_miibus);
2314 xl_stats_update(sc);
2315 if (xl_watchdog(sc) == EJUSTRETURN)
2318 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2322 xl_stats_update(struct xl_softc *sc)
2324 struct ifnet *ifp = sc->xl_ifp;
2329 XL_LOCK_ASSERT(sc);
2339 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2355 CSR_READ_1(sc, XL_W4_BADSSD);
2364 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2367 struct ifnet *ifp = sc->xl_ifp;
2371 XL_LOCK_ASSERT(sc);
2373 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2374 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2398 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2399 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2415 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2419 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2422 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2424 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2425 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2429 if (sc->xl_type == XL_TYPE_905B) {
2461 struct xl_softc *sc = ifp->if_softc;
2463 XL_LOCK(sc);
2465 if (sc->xl_type == XL_TYPE_905B)
2470 XL_UNLOCK(sc);
2476 struct xl_softc *sc = ifp->if_softc;
2482 XL_LOCK_ASSERT(sc);
2491 if (sc->xl_cdata.xl_tx_free == NULL) {
2492 xl_txeoc(sc);
2493 xl_txeof(sc);
2494 if (sc->xl_cdata.xl_tx_free == NULL) {
2500 start_tx = sc->xl_cdata.xl_tx_free;
2503 sc->xl_cdata.xl_tx_free != NULL;) {
2510 cur_tx = sc->xl_cdata.xl_tx_free;
2513 error = xl_encap(sc, cur_tx, &m_head);
2523 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2559 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2560 xl_wait(sc);
2562 if (sc->xl_cdata.xl_tx_head != NULL) {
2563 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2564 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2566 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2568 sc->xl_cdata.xl_tx_tail = cur_tx;
2570 sc->xl_cdata.xl_tx_head = start_tx;
2571 sc->xl_cdata.xl_tx_tail = cur_tx;
2573 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2575 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2576 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2578 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2585 sc->xl_wdog_timer = 5;
2602 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2608 struct xl_softc *sc = ifp->if_softc;
2614 XL_LOCK_ASSERT(sc);
2620 idx = sc->xl_cdata.xl_tx_prod;
2621 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2624 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2625 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2635 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2638 error = xl_encap(sc, cur_tx, &m_head);
2660 sc->xl_cdata.xl_tx_cnt++;
2679 sc->xl_cdata.xl_tx_prod = idx;
2681 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2687 sc->xl_wdog_timer = 5;
2693 struct xl_softc *sc = xsc;
2695 XL_LOCK(sc);
2696 xl_init_locked(sc);
2697 XL_UNLOCK(sc);
2701 xl_init_locked(struct xl_softc *sc)
2703 struct ifnet *ifp = sc->xl_ifp;
2707 XL_LOCK_ASSERT(sc);
2714 xl_stop(sc);
2717 xl_reset(sc);
2719 if (sc->xl_miibus == NULL) {
2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2721 xl_wait(sc);
2723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2724 xl_wait(sc);
2727 if (sc->xl_miibus != NULL)
2728 mii = device_get_softc(sc->xl_miibus);
2734 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2736 CSR_READ_2(sc, XL_W7_BM_PME);
2737 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2742 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2743 IF_LLADDR(sc->xl_ifp)[i]);
2748 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2751 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2752 xl_wait(sc);
2753 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2754 xl_wait(sc);
2757 error = xl_list_rx_init(sc);
2759 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2761 xl_stop(sc);
2766 if (sc->xl_type == XL_TYPE_905B)
2767 error = xl_list_tx_init_90xB(sc);
2769 error = xl_list_tx_init(sc);
2771 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2773 xl_stop(sc);
2783 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2797 if (sc->xl_type == XL_TYPE_905B) {
2798 CSR_WRITE_2(sc, XL_COMMAND,
2803 xl_rxfilter(sc);
2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2816 xl_wait(sc);
2817 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2819 xl_wait(sc);
2821 if (sc->xl_type == XL_TYPE_905B) {
2823 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2826 xl_wait(sc);
2827 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2828 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2829 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2830 xl_wait(sc);
2838 if (sc->xl_xcvr == XL_XCVR_COAX)
2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2850 if (sc->xl_type == XL_TYPE_905B)
2851 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2854 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2856 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2861 xl_stats_update(sc);
2863 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2878 if (sc->xl_flags & XL_FLAG_FUNCREG)
2879 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2883 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2887 xl_wait(sc);
2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2889 xl_wait(sc);
2901 sc->xl_wdog_timer = 0;
2902 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2911 struct xl_softc *sc = ifp->if_softc;
2915 XL_LOCK(sc);
2917 if (sc->xl_miibus != NULL)
2918 mii = device_get_softc(sc->xl_miibus);
2920 ifm = &sc->ifmedia;
2929 xl_setmode(sc, ifm->ifm_media);
2930 XL_UNLOCK(sc);
2934 if (sc->xl_media & XL_MEDIAOPT_MII ||
2935 sc->xl_media & XL_MEDIAOPT_BTX ||
2936 sc->xl_media & XL_MEDIAOPT_BT4) {
2938 xl_init_locked(sc);
2940 xl_setmode(sc, ifm->ifm_media);
2943 XL_UNLOCK(sc);
2954 struct xl_softc *sc = ifp->if_softc;
2959 XL_LOCK(sc);
2961 if (sc->xl_miibus != NULL)
2962 mii = device_get_softc(sc->xl_miibus);
2965 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2968 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2980 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2986 if (sc->xl_type == XL_TYPE_905B &&
2987 sc->xl_media == XL_MEDIAOPT_10FL) {
2989 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3020 XL_UNLOCK(sc);
3026 struct xl_softc *sc = ifp->if_softc;
3033 XL_LOCK(sc);
3036 (ifp->if_flags ^ sc->xl_if_flags) &
3038 xl_rxfilter(sc);
3040 xl_init_locked(sc);
3043 xl_stop(sc);
3045 sc->xl_if_flags = ifp->if_flags;
3046 XL_UNLOCK(sc);
3051 XL_LOCK(sc);
3053 xl_rxfilter(sc);
3054 XL_UNLOCK(sc);
3058 if (sc->xl_miibus != NULL)
3059 mii = device_get_softc(sc->xl_miibus);
3062 &sc->ifmedia, command);
3077 XL_LOCK(sc);
3079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3081 XL_UNLOCK(sc);
3085 XL_LOCK(sc);
3086 CSR_WRITE_2(sc, XL_COMMAND,
3088 CSR_WRITE_2(sc, XL_COMMAND,
3090 if (sc->xl_flags & XL_FLAG_FUNCREG)
3091 bus_space_write_4(sc->xl_ftag,
3092 sc->xl_fhandle, 4, 0x8000);
3093 XL_UNLOCK(sc);
3097 XL_LOCK(sc);
3112 XL_UNLOCK(sc);
3123 xl_watchdog(struct xl_softc *sc)
3125 struct ifnet *ifp = sc->xl_ifp;
3129 XL_LOCK_ASSERT(sc);
3131 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3134 xl_rxeof(sc);
3135 xl_txeoc(sc);
3137 if (sc->xl_type == XL_TYPE_905B) {
3138 xl_txeof_90xB(sc);
3139 if (sc->xl_cdata.xl_tx_cnt == 0)
3142 xl_txeof(sc);
3143 if (sc->xl_cdata.xl_tx_head == NULL)
3147 device_printf(sc->xl_dev,
3154 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3155 device_printf(sc->xl_dev, "watchdog timeout\n");
3158 device_printf(sc->xl_dev,
3162 xl_init_locked(sc);
3165 if (sc->xl_type == XL_TYPE_905B)
3179 xl_stop(struct xl_softc *sc)
3182 struct ifnet *ifp = sc->xl_ifp;
3184 XL_LOCK_ASSERT(sc);
3186 sc->xl_wdog_timer = 0;
3188 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3189 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3192 xl_wait(sc);
3193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3198 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3199 xl_wait(sc);
3200 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3201 xl_wait(sc);
3204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3206 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3207 if (sc->xl_flags & XL_FLAG_FUNCREG)
3208 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3211 callout_stop(&sc->xl_tick_callout);
3217 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3218 bus_dmamap_unload(sc->xl_mtag,
3219 sc->xl_cdata.xl_rx_chain[i].xl_map);
3220 bus_dmamap_destroy(sc->xl_mtag,
3221 sc->xl_cdata.xl_rx_chain[i].xl_map);
3222 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3223 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3226 if (sc->xl_ldata.xl_rx_list != NULL)
3227 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3232 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3233 bus_dmamap_unload(sc->xl_mtag,
3234 sc->xl_cdata.xl_tx_chain[i].xl_map);
3235 bus_dmamap_destroy(sc->xl_mtag,
3236 sc->xl_cdata.xl_tx_chain[i].xl_map);
3237 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3238 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3241 if (sc->xl_ldata.xl_tx_list != NULL)
3242 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3261 struct xl_softc *sc;
3263 sc = device_get_softc(dev);
3265 XL_LOCK(sc);
3266 xl_stop(sc);
3267 xl_setwol(sc);
3268 XL_UNLOCK(sc);
3276 struct xl_softc *sc;
3279 sc = device_get_softc(dev);
3280 ifp = sc->xl_ifp;
3282 XL_LOCK(sc);
3286 xl_init_locked(sc);
3289 XL_UNLOCK(sc);
3295 xl_setwol(struct xl_softc *sc)
3300 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3303 ifp = sc->xl_ifp;
3306 CSR_READ_2(sc, XL_W7_BM_PME);
3310 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3315 pmstat = pci_read_config(sc->xl_dev,
3316 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3321 pci_write_config(sc->xl_dev,
3322 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);