accelerants/intel_extreme/Ports.cpp

1020 	TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
1021 		target->timing.v_display);
1031 		fitter->Enable(target->timing);
1037 		link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1038 		fPipe->SetFDILink(target->timing, linkBandwidth, lanes, bitsPerPixel);
1039 		link->Train(&target->timing, lanes);
1042 	compute_pll_divisors(&target->timing, &divisors, false);
1052 	fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1056 		| ((target->timing.flags & B_POSITIVE_HSYNC) != 0
1058 		| ((target->timing.flags & B_POSITIVE_VSYNC) != 0
1207 		target->timing.h_display, target->timing.v_display);
1248 		if (hardwareTarget.h_display == target->timing.h_display
1249 				&& hardwareTarget.v_display == target->timing.v_display) {
1251 			// Note: this means refresh and timing might vary according to requested mode.
1252 			hardwareTarget = target->timing;
1270 		hardwareTarget = target->timing;
1324 	if ((target->timing.flags & B_POSITIVE_HSYNC) == 0)
1326 	if ((target->timing.flags & B_POSITIVE_VSYNC) == 0)
1468 	TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
1469 		target->timing.v_display);
1479 		fitter->Enable(target->timing);
1485 		link->PreTrain(&target->timing, &linkBandwidth, &lanes, &bitsPerPixel);
1486 		fPipe->SetFDILink(target->timing, linkBandwidth, lanes, bitsPerPixel);
1487 		link->Train(&target->timing, lanes);
1491 	compute_pll_divisors(&target->timing, &divisors, false);
1501 	fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1839 DisplayPort::_SetPortLinkGen4(const display_timing& timing)
1865 	uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1883 	ret_m = timing.pixel_clock * ret_n / linkspeed;
1902 DisplayPort::_SetPortLinkGen6(const display_timing& timing)
1955 	uint32 bps = timing.pixel_clock * bitsPerPixel * 21 / 20;
1974 	uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1992 	ret_m = timing.pixel_clock * ret_n / linkspeed;
2014 	TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
2015 		target->timing.v_display);
2025 		result = _SetPortLinkGen4(target->timing);
2027 		display_timing hardwareTarget = target->timing;
2039 				if (hardwareTarget.h_display == target->timing.h_display
2040 						&& hardwareTarget.v_display == target->timing.v_display) {
2049 				//fixme: We should now first try for EDID info detailed timing, highest res in list: that's the
2056 				hardwareTarget = target->timing;
2465 DigitalDisplayInterface::_SetPortLinkGen8(const display_timing& timing, uint32 pllSel)
2563 	uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
2581 	ret_m = timing.pixel_clock * ret_n / linkspeed;
2602 	TRACE("%s: %s %dx%d\n", __func__, PortName(), target->timing.h_display,
2603 		target->timing.v_display);
2610 	display_timing hardwareTarget = target->timing;
2621 				// the first detailed timing supposed to be the best supported one
2629 					TRACE("%s: Using EDID detailed timing %d for the internal panel\n",
2631 					const edid1_detailed_timing& timing
2633 					hardwareTarget.pixel_clock = timing.pixel_clock * 10;
2634 					hardwareTarget.h_display = timing.h_active;
2635 					hardwareTarget.h_sync_start = timing.h_active + timing.h_sync_off;
2636 					hardwareTarget.h_sync_end = hardwareTarget.h_sync_start + timing.h_sync_width;
2637 					hardwareTarget.h_total = timing.h_active + timing.h_blank;
2638 					hardwareTarget.v_display = timing.v_active;
2639 					hardwareTarget.v_sync_start = timing.v_active + timing.v_sync_off;
2640 					hardwareTarget.v_sync_end = hardwareTarget.v_sync_start + timing.v_sync_width;
2641 					hardwareTarget.v_total = timing.v_active + timing.v_blank;
2643 					if (timing.sync == 3) {
2644 						if (timing.misc & 1)
2646 						if (timing.misc & 2)
2649 					if (timing.interlaced)
2653 			if (hardwareTarget.h_display == target->timing.h_display
2654 					&& hardwareTarget.v_display == target->timing.v_display) {
2656 				// Note: this means refresh and timing might vary according to requested mode.
2657 				hardwareTarget = target->timing;
2675 			hardwareTarget = target->timing;