accelerants/intel_extreme/Pipes.cpp

198 		TRACE("%s: trans conf reg: 0x%" B_PRIx32"\n", __func__,
200 		TRACE("%s: trans DDI func ctl reg: 0x%" B_PRIx32"\n", __func__,
226 	TRACE("%s: FDI/PIPE M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset));
227 	TRACE("%s: FDI/PIPE N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset));
228 	TRACE("%s: FDI/PIPE M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset));
229 	TRACE("%s: FDI/PIPE N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset));
241 	TRACE("%s: FDI/PIPE link with %" B_PRIx32 " lane(s) in use\n", __func__, lanes);
279 	TRACE("%s: FDI/PIPE M1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset));
280 	TRACE("%s: FDI/PIPE N1 data after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset));
281 	TRACE("%s: FDI/PIPE M1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_M1 + fPipeOffset));
282 	TRACE("%s: FDI/PIPE N1 link after: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_LINK_N1 + fPipeOffset));
507 		TRACE("Old PLL selection: 0x%" B_PRIx32 "\n", pllSel);
532 		TRACE("New PLL selection: 0x%" B_PRIx32 "\n", pllSel);
566 	TRACE("PLL selected is %" B_PRIx32 "\n", *pllSel);
568 	TRACE("Skylake DPLL_CFGCR1 0x%" B_PRIx32 "\n",
570 	TRACE("Skylake DPLL_CFGCR2 0x%" B_PRIx32 "\n",
600 		TRACE("Skylake DPLL_CFGCR1 now: 0x%" B_PRIx32 "\n",
602 		TRACE("Skylake DPLL_CFGCR2 now: 0x%" B_PRIx32 "\n",
608 	TRACE("Skylake DPLL_CTRL1: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL1));
609 	TRACE("Skylake DPLL_CTRL2: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_CTRL2));
610 	TRACE("Skylake DPLL_STATUS: 0x%" B_PRIx32 "\n", read32(SKL_DPLL_STATUS));