accelerants/intel_extreme/Pipes.cpp

167 		// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
169 			((uint32)(target->timing.h_total - 1) << 16)
170 			| ((uint32)target->timing.h_display - 1));
172 			((uint32)(target->timing.h_total - 1) << 16)
173 			| ((uint32)target->timing.h_display - 1));
175 			((uint32)(target->timing.h_sync_end - 1) << 16)
176 			| ((uint32)target->timing.h_sync_start - 1));
179 			((uint32)(target->timing.v_total - 1) << 16)
180 			| ((uint32)target->timing.v_display - 1));
182 			((uint32)(target->timing.v_total - 1) << 16)
183 			| ((uint32)target->timing.v_display - 1));
185 			((uint32)(target->timing.v_sync_end - 1) << 16)
186 			| ((uint32)target->timing.v_sync_start - 1));
192 			((uint32)(target->timing.h_display - 1) << 16)
193 				| ((uint32)target->timing.v_display - 1));
196 		//on Skylake timing is already done in ConfigureTimings()
222 Pipe::SetFDILink(const display_timing& timing, uint32 linkBandwidth, uint32 lanes, uint32 bitsPerPixel)
252 	uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
270 	ret_m = timing.pixel_clock * ret_n / linkspeed;
312 		((uint32)(target->timing.h_display - 1) << 16)
313 			| ((uint32)target->timing.v_display - 1));
326 			((uint32)(target->timing.v_display - 1) << 16)
327 			| ((uint32)target->timing.h_display - 1));
350 		// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
353 			((uint32)(target->timing.h_total - 1) << 16)
354 			| ((uint32)target->timing.h_display - 1));
356 			((uint32)(target->timing.h_total - 1) << 16)
357 			| ((uint32)target->timing.h_display - 1));
359 			((uint32)(target->timing.h_sync_end - 1) << 16)
360 			| ((uint32)target->timing.h_sync_start - 1));
363 			((uint32)(target->timing.v_total - 1) << 16)
364 			| ((uint32)target->timing.v_display - 1));
366 			((uint32)(target->timing.v_total - 1) << 16)
367 			| ((uint32)target->timing.v_display - 1));
369 			((uint32)(target->timing.v_sync_end - 1) << 16)
370 			| ((uint32)target->timing.v_sync_start - 1));