Lines Matching refs:REGS_SOUTH_SHARED
148 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT)
1273 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
1296 #define PCH_RAWCLK_FREQ (0x6204 | REGS_SOUTH_SHARED)
1301 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
1302 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
1303 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
1304 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
1305 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
1306 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
1308 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
1309 #define INTEL_DISPLAY_A_PLL_DIVISOR_1 (0x6044 | REGS_SOUTH_SHARED)
1310 #define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
1311 #define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
1313 #define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED)
1316 #define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED)
1317 #define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED)
1318 #define INTEL_I2C_IO_C (0x5018 | REGS_SOUTH_SHARED)
1319 #define INTEL_I2C_IO_D (0x501c | REGS_SOUTH_SHARED)
1320 #define INTEL_I2C_IO_E (0x5020 | REGS_SOUTH_SHARED)
1321 #define INTEL_I2C_IO_F (0x5024 | REGS_SOUTH_SHARED)
1322 #define INTEL_I2C_IO_G (0x5028 | REGS_SOUTH_SHARED)
1323 #define INTEL_I2C_IO_H (0x502c | REGS_SOUTH_SHARED)
1324 #define INTEL_I2C_IO_I (0x5030 | REGS_SOUTH_SHARED)
1325 #define INTEL_I2C_IO_J (0x5034 | REGS_SOUTH_SHARED)
1326 #define INTEL_I2C_IO_K (0x5038 | REGS_SOUTH_SHARED)
1327 #define INTEL_I2C_IO_L (0x503c | REGS_SOUTH_SHARED)
1328 #define INTEL_I2C_IO_M (0x5040 | REGS_SOUTH_SHARED)
1329 #define INTEL_I2C_IO_N (0x5044 | REGS_SOUTH_SHARED)
1331 #define INTEL_GMBUS0 (0x5100 | REGS_SOUTH_SHARED)
1332 #define INTEL_GMBUS4 (0x5110 | REGS_SOUTH_SHARED)
1347 #define INTEL_DSPCLK_GATE_D (0x2020 | REGS_SOUTH_SHARED)
1388 #define PCH_PANEL_STATUS (0x7200 | REGS_SOUTH_SHARED)
1389 #define PCH_PANEL_CONTROL (0x7204 | REGS_SOUTH_SHARED)
1390 #define PCH_PANEL_ON_DELAYS (0x7208 | REGS_SOUTH_SHARED)
1391 #define PCH_PANEL_OFF_DELAYS (0x720c | REGS_SOUTH_SHARED)
1392 #define PCH_PANEL_DIVISOR (0x7210 | REGS_SOUTH_SHARED)
1422 #define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31
1423 #define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period
1427 #define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
1428 #define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
1429 #define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
1641 #define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED)
1642 #define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED)
1646 #define SFUSE_STRAP (0x2014 | REGS_SOUTH_SHARED)