graphics/intel_extreme/intel_extreme.h

497 	bool HasPipe(pipe_index pipe)
499 		if (pipe == INTEL_PIPE_ANY)
502 		return (bitmask & (1 << pipe)) != 0;
505 	void SetPipe(pipe_index pipe)
507 		if (pipe == INTEL_PIPE_ANY) {
512 		bitmask |= (1 << pipe);
515 	void ClearPipe(pipe_index pipe)
517 		if (pipe == INTEL_PIPE_ANY)
520 		bitmask &= ~(1 << pipe);
746 // the introduction of pipe C.
753 #define PCH_MASTER_INT_CTL_PIPE_PENDING_BDW(pipe)	(1 << (15 + pipe))
758 #define PCH_INTERRUPT_PIPE_STATUS_BDW(pipe)		(0x44400 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_ISR
759 #define PCH_INTERRUPT_PIPE_MASK_BDW(pipe)		(0x44404 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IMR
760 #define PCH_INTERRUPT_PIPE_IDENTITY_BDW(pipe)	(0x44408 + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IIR
761 #define PCH_INTERRUPT_PIPE_ENABLED_BDW(pipe)	(0x4440c + (pipe - 1) * 0x10)	// GEN8_DE_PIPE_IER
843 // Cougar Point transcoder pipe selection
1415 // These have moved around, initially they were per pipe, then they were moved in the "north" part
1432 	// Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be
1433 	// programmed for use on either pipe)
1481 // PCH for each display pipe.
1486 #define FDI_RX_CTL(pipe)				(_FDI_RXA_CTL + (_FDI_RXB_CTL - _FDI_RXA_CTL) * (pipe - INTEL_PIPE_A))
1489 #define FDI_RX_MISC(pipe)				(_FDI_RXA_MISC + (_FDI_RXB_MISC - _FDI_RXA_MISC) * (pipe - INTEL_PIPE_A))
1492 #define FDI_RX_IIR(pipe)				(_FDI_RXA_IIR + (_FDI_RXB_IIR - _FDI_RXA_IIR) * (pipe - INTEL_PIPE_A))
1495 #define FDI_RX_IMR(pipe)				(_FDI_RXA_IMR + (_FDI_RXB_IMR - _FDI_RXA_IMR) * (pipe - INTEL_PIPE_A))
1538 #define FDI_RX_TUSIZE1(pipe)	(_FDI_RXA_TUSIZE1 + (_FDI_RXB_TUSIZE1 - _FDI_RXA_TUSIZE1) * (pipe - INTEL_PIPE_A))
1539 #define FDI_RX_TUSIZE2(pipe)	(_FDI_RXA_TUSIZE2 + (_FDI_RXB_TUSIZE2 - _FDI_RXA_TUSIZE2) * (pipe - INTEL_PIPE_A))
1559 #define FDI_TX_CTL(pipe)				(_FDI_TXA_CTL + (_FDI_TXB_CTL - _FDI_TXA_CTL) * (pipe - INTEL_PIPE_A))