Lines Matching refs:sc
358 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
359 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
360 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
361 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
362 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
363 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
364 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
386 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
535 bge_has_eaddr(struct bge_softc *sc)
542 dev = sc->bge_dev;
573 bge_readmem_ind(struct bge_softc *sc, int off)
578 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
582 dev = sc->bge_dev;
591 bge_writemem_ind(struct bge_softc *sc, int off, int val)
595 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
599 dev = sc->bge_dev;
608 bge_readreg_ind(struct bge_softc *sc, int off)
612 dev = sc->bge_dev;
620 bge_writereg_ind(struct bge_softc *sc, int off, int val)
624 dev = sc->bge_dev;
631 bge_writemem_direct(struct bge_softc *sc, int off, int val)
633 CSR_WRITE_4(sc, off, val);
641 bge_writembx(struct bge_softc *sc, int off, int val)
643 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
646 CSR_WRITE_4(sc, off, val);
647 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
648 CSR_READ_4(sc, off);
670 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
676 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
678 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
686 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
687 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
689 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
690 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
693 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
700 if_printf(sc->bge_ifp, "nvram read timed out\n");
705 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
710 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
713 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
714 CSR_READ_4(sc, BGE_NVRAM_SWARB);
723 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
728 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
732 err = bge_nvram_getbyte(sc, off + i, &byte);
748 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
757 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
760 CSR_WRITE_4(sc, BGE_EE_ADDR,
765 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
770 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
775 device_printf(sc->bge_dev, "EEPROM read timed out\n");
780 byte = CSR_READ_4(sc, BGE_EE_DATA);
791 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
797 error = bge_eeprom_getbyte(sc, off + i, &byte);
809 struct bge_softc *sc;
813 sc = device_get_softc(dev);
816 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
817 CSR_WRITE_4(sc, BGE_MI_MODE,
818 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
822 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
828 val = CSR_READ_4(sc, BGE_MI_COMM);
831 val = CSR_READ_4(sc, BGE_MI_COMM);
837 device_printf(sc->bge_dev,
844 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
845 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
858 struct bge_softc *sc;
861 sc = device_get_softc(dev);
863 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
868 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
869 CSR_WRITE_4(sc, BGE_MI_MODE,
870 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
874 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
879 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
881 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
887 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
888 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
893 device_printf(sc->bge_dev,
903 struct bge_softc *sc;
905 sc = device_get_softc(dev);
906 mii = device_get_softc(sc->bge_miibus);
913 sc->bge_link = 1;
918 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
919 sc->bge_link = 1;
921 sc->bge_link = 0;
924 sc->bge_link = 0;
928 sc->bge_link = 0;
929 if (sc->bge_link == 0)
931 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
934 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
936 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
939 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
942 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
944 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
947 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
949 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
951 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
952 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
953 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
961 bge_newbuf_std(struct bge_softc *sc, int i)
969 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
970 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
982 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
985 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
986 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
991 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
992 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
993 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
994 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
995 sc->bge_cdata.bge_rx_std_dmamap[i]);
997 map = sc->bge_cdata.bge_rx_std_dmamap[i];
998 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
999 sc->bge_cdata.bge_rx_std_sparemap = map;
1000 sc->bge_cdata.bge_rx_std_chain[i] = m;
1001 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1002 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1009 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1010 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1020 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1038 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1041 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1042 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1048 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1049 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1050 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1051 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1052 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1054 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1055 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1056 sc->bge_cdata.bge_rx_jumbo_sparemap;
1057 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1058 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1059 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1060 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1061 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1062 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1067 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1076 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1081 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1086 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1091 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1097 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1098 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1104 bge_init_rx_ring_std(struct bge_softc *sc)
1108 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1109 sc->bge_std = 0;
1111 if ((error = bge_newbuf_std(sc, i)) != 0)
1113 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1116 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1117 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1119 sc->bge_std = 0;
1120 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1126 bge_free_rx_ring_std(struct bge_softc *sc)
1131 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1132 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1133 sc->bge_cdata.bge_rx_std_dmamap[i],
1135 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1136 sc->bge_cdata.bge_rx_std_dmamap[i]);
1137 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1138 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1140 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1146 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1151 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1152 sc->bge_jumbo = 0;
1154 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1156 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1159 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1160 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1162 sc->bge_jumbo = 0;
1165 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1168 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1170 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1176 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1181 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1182 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1183 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1185 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1186 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1187 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1188 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1190 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1196 bge_free_tx_ring(struct bge_softc *sc)
1200 if (sc->bge_ldata.bge_tx_ring == NULL)
1204 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1205 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1206 sc->bge_cdata.bge_tx_dmamap[i],
1208 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1209 sc->bge_cdata.bge_tx_dmamap[i]);
1210 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1211 sc->bge_cdata.bge_tx_chain[i] = NULL;
1213 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1219 bge_init_tx_ring(struct bge_softc *sc)
1221 sc->bge_txcnt = 0;
1222 sc->bge_tx_saved_considx = 0;
1224 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1225 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1226 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1229 sc->bge_tx_prodidx = 0;
1230 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1233 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1234 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1237 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1239 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1240 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1246 bge_setpromisc(struct bge_softc *sc)
1250 BGE_LOCK_ASSERT(sc);
1252 ifp = sc->bge_ifp;
1256 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1258 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1262 bge_setmulti(struct bge_softc *sc)
1269 BGE_LOCK_ASSERT(sc);
1271 ifp = sc->bge_ifp;
1275 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1281 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1295 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1299 bge_setvlan(struct bge_softc *sc)
1303 BGE_LOCK_ASSERT(sc);
1305 ifp = sc->bge_ifp;
1309 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1311 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1315 bge_sig_pre_reset(struct bge_softc *sc, int type)
1321 if (sc->bge_asf_mode)
1322 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1324 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1327 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1331 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1339 bge_sig_post_reset(struct bge_softc *sc, int type)
1342 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1345 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1350 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1358 bge_sig_legacy(struct bge_softc *sc, int type)
1361 if (sc->bge_asf_mode) {
1364 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1368 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1376 bge_stop_fw(struct bge_softc *sc)
1380 if (sc->bge_asf_mode) {
1381 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1382 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1383 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1386 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1395 bge_dma_swap_options(struct bge_softc *sc)
1404 if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720)
1416 bge_chipinit(struct bge_softc *sc)
1424 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1426 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1429 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1437 BGE_MEMWIN_WRITE(sc, i, 0);
1441 BGE_MEMWIN_WRITE(sc, i, 0);
1443 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1449 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1451 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1459 if (sc->bge_flags & BGE_FLAG_PCIE) {
1462 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1463 if (BGE_IS_5714_FAMILY(sc)) {
1467 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1470 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1479 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1489 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1490 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1494 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1507 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1508 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1511 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1512 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1515 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1516 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1518 if (BGE_IS_5717_PLUS(sc)) {
1520 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1527 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1528 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1531 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1536 mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1545 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1546 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1552 if (sc->bge_asf_mode & ASF_STACKUP)
1555 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1562 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1566 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1569 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1573 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1574 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1582 bge_blockinit(struct bge_softc *sc)
1596 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1600 if (!(BGE_IS_5705_PLUS(sc))) {
1602 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1603 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1604 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1606 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1609 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1611 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1615 if (BGE_IS_5717_PLUS(sc)) {
1616 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1617 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1618 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1619 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1621 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1622 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1624 } else if (!BGE_IS_5705_PLUS(sc)) {
1625 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1626 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1627 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1628 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1629 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1630 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1631 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1633 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1634 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1635 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1639 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1640 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1650 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1652 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1657 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1662 device_printf(sc->bge_dev, "buffer manager failed to start\n");
1667 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1668 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1673 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1678 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1714 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1716 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1718 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1719 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1720 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1721 if (BGE_IS_5717_PLUS(sc)) {
1730 } else if (BGE_IS_5705_PLUS(sc)) {
1749 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1750 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1751 sc->bge_asicrev == BGE_ASICREV_BCM5720)
1756 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1757 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1758 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1759 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1762 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1771 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1772 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1775 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1777 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1778 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1779 sc->bge_cdata.bge_rx_jumbo_ring_map,
1783 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1784 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1785 sc->bge_asicrev == BGE_ASICREV_BCM5720)
1789 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1791 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1794 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1796 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1798 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1802 if (BGE_IS_5700_FAMILY(sc)) {
1803 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1806 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1809 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1813 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1814 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1815 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1816 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
1817 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1818 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1837 if (BGE_IS_5705_PLUS(sc))
1841 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1842 if (BGE_IS_JUMBO_CAPABLE(sc))
1843 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1845 if (BGE_IS_5717_PLUS(sc)) {
1846 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1847 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1855 if (!BGE_IS_5705_PLUS(sc))
1862 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1864 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1870 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1871 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1872 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1873 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1874 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1875 sc->bge_asicrev == BGE_ASICREV_BCM5720)
1876 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1878 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1880 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1888 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1889 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1890 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
1893 } else if (!BGE_IS_5705_PLUS(sc))
1895 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1896 sc->bge_asicrev == BGE_ASICREV_BCM57765)
1903 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1904 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1905 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1907 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1908 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1919 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1920 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1921 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1922 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1923 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1924 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1927 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1928 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1929 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1930 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1935 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
1936 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1938 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1944 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1950 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1953 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1954 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1957 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1962 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1967 device_printf(sc->bge_dev,
1973 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1974 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1975 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1976 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1977 if (!(BGE_IS_5705_PLUS(sc))) {
1978 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1979 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1981 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1982 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1985 if (!(BGE_IS_5705_PLUS(sc))) {
1986 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1987 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1988 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1989 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1990 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1991 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1992 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1996 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1997 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1998 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1999 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2002 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2003 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2005 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2008 bzero(sc->bge_ldata.bge_status_block, 32);
2010 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2011 sc->bge_cdata.bge_status_map,
2015 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2018 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2022 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2025 if (!(BGE_IS_5705_PLUS(sc)))
2026 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2033 if (sc->bge_flags & BGE_FLAG_TBI)
2035 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2041 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2044 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2048 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2050 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2055 if (!(BGE_IS_5705_PLUS(sc)))
2056 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2061 if (BGE_IS_5755_PLUS(sc))
2065 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2069 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2075 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2078 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2079 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2080 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2084 if (sc->bge_flags & BGE_FLAG_PCIE)
2086 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2088 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2089 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2090 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2094 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2095 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2104 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2105 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2106 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2107 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2108 BGE_IS_5717_PLUS(sc)) {
2109 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2114 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2115 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2128 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2132 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2133 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2134 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2137 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2142 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2143 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2148 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2152 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2155 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2158 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2161 if (!(BGE_IS_5705_PLUS(sc)))
2162 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2165 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2169 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2171 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2174 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2175 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2178 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2181 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2184 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2186 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2187 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2191 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2194 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2200 if (sc->bge_flags & BGE_FLAG_TBI) {
2201 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2203 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2204 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2207 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2208 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2209 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2220 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2225 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2278 struct bge_softc *sc = device_get_softc(dev);
2284 sc->bge_dev = dev;
2320 if (bge_has_eaddr(sc) &&
2339 bge_dma_free(struct bge_softc *sc)
2345 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2346 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2347 sc->bge_cdata.bge_rx_std_dmamap[i]);
2349 if (sc->bge_cdata.bge_rx_std_sparemap)
2350 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2351 sc->bge_cdata.bge_rx_std_sparemap);
2355 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2356 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2357 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2359 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2360 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2361 sc->bge_cdata.bge_rx_jumbo_sparemap);
2365 if (sc->bge_cdata.bge_tx_dmamap[i])
2366 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2367 sc->bge_cdata.bge_tx_dmamap[i]);
2370 if (sc->bge_cdata.bge_rx_mtag)
2371 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2372 if (sc->bge_cdata.bge_mtag_jumbo)
2373 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2374 if (sc->bge_cdata.bge_tx_mtag)
2375 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2378 if (sc->bge_cdata.bge_rx_std_ring_map)
2379 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2380 sc->bge_cdata.bge_rx_std_ring_map);
2381 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2382 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2383 sc->bge_ldata.bge_rx_std_ring,
2384 sc->bge_cdata.bge_rx_std_ring_map);
2386 if (sc->bge_cdata.bge_rx_std_ring_tag)
2387 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2390 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2391 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2392 sc->bge_cdata.bge_rx_jumbo_ring_map);
2394 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2395 sc->bge_ldata.bge_rx_jumbo_ring)
2396 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2397 sc->bge_ldata.bge_rx_jumbo_ring,
2398 sc->bge_cdata.bge_rx_jumbo_ring_map);
2400 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2401 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2404 if (sc->bge_cdata.bge_rx_return_ring_map)
2405 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2406 sc->bge_cdata.bge_rx_return_ring_map);
2408 if (sc->bge_cdata.bge_rx_return_ring_map &&
2409 sc->bge_ldata.bge_rx_return_ring)
2410 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2411 sc->bge_ldata.bge_rx_return_ring,
2412 sc->bge_cdata.bge_rx_return_ring_map);
2414 if (sc->bge_cdata.bge_rx_return_ring_tag)
2415 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2418 if (sc->bge_cdata.bge_tx_ring_map)
2419 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2420 sc->bge_cdata.bge_tx_ring_map);
2422 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2423 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2424 sc->bge_ldata.bge_tx_ring,
2425 sc->bge_cdata.bge_tx_ring_map);
2427 if (sc->bge_cdata.bge_tx_ring_tag)
2428 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2431 if (sc->bge_cdata.bge_status_map)
2432 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2433 sc->bge_cdata.bge_status_map);
2435 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2436 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2437 sc->bge_ldata.bge_status_block,
2438 sc->bge_cdata.bge_status_map);
2440 if (sc->bge_cdata.bge_status_tag)
2441 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2444 if (sc->bge_cdata.bge_stats_map)
2445 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2446 sc->bge_cdata.bge_stats_map);
2448 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2449 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2450 sc->bge_ldata.bge_stats,
2451 sc->bge_cdata.bge_stats_map);
2453 if (sc->bge_cdata.bge_stats_tag)
2454 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2456 if (sc->bge_cdata.bge_buffer_tag)
2457 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2460 if (sc->bge_cdata.bge_parent_tag)
2461 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2465 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2476 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2480 device_printf(sc->bge_dev,
2488 device_printf(sc->bge_dev,
2497 device_printf(sc->bge_dev,
2503 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2513 device_printf(sc->bge_dev, "4GB boundary crossed, "
2525 bge_dma_alloc(struct bge_softc *sc)
2532 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2537 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2540 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2542 device_printf(sc->bge_dev,
2548 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2549 &sc->bge_cdata.bge_rx_std_ring_tag,
2550 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2551 &sc->bge_cdata.bge_rx_std_ring_map,
2552 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2557 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2558 &sc->bge_cdata.bge_rx_return_ring_tag,
2559 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2560 &sc->bge_cdata.bge_rx_return_ring_map,
2561 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2566 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2567 &sc->bge_cdata.bge_tx_ring_tag,
2568 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2569 &sc->bge_cdata.bge_tx_ring_map,
2570 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2581 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2582 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2586 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2587 &sc->bge_cdata.bge_status_tag,
2588 (uint8_t **)&sc->bge_ldata.bge_status_block,
2589 &sc->bge_cdata.bge_status_map,
2590 &sc->bge_ldata.bge_status_block_paddr, "status block");
2595 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2596 &sc->bge_cdata.bge_stats_tag,
2597 (uint8_t **)&sc->bge_ldata.bge_stats,
2598 &sc->bge_cdata.bge_stats_map,
2599 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2604 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2605 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2606 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2607 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2608 &sc->bge_cdata.bge_rx_jumbo_ring_map,
2609 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2616 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2625 if (sc->bge_pcixcap != 0)
2628 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2631 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2633 device_printf(sc->bge_dev,
2638 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2645 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2648 &sc->bge_cdata.bge_tx_mtag);
2651 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2656 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
2660 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
2662 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2665 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2670 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2671 &sc->bge_cdata.bge_rx_std_sparemap);
2673 device_printf(sc->bge_dev,
2678 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2679 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2681 device_printf(sc->bge_dev,
2689 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2690 &sc->bge_cdata.bge_tx_dmamap[i]);
2692 device_printf(sc->bge_dev,
2699 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2700 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
2703 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2705 device_printf(sc->bge_dev,
2710 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2711 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2713 device_printf(sc->bge_dev,
2718 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2719 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2721 device_printf(sc->bge_dev,
2735 bge_has_multiple_ports(struct bge_softc *sc)
2737 device_t dev = sc->bge_dev;
2754 bge_can_use_msi(struct bge_softc *sc)
2764 if (sc->bge_msi == 0)
2771 switch (sc->bge_asicrev) {
2778 if (bge_has_multiple_ports(sc))
2782 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2783 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2787 if (BGE_IS_575X_PLUS(sc))
2794 bge_mbox_reorder(struct bge_softc *sc)
2811 dev = sc->bge_dev;
2823 device_printf(sc->bge_dev,
2837 bge_devinfo(struct bge_softc *sc)
2841 device_printf(sc->bge_dev,
2843 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
2844 if (sc->bge_flags & BGE_FLAG_PCIE)
2846 else if (sc->bge_flags & BGE_FLAG_PCIX) {
2848 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2852 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
2873 if (sc->bge_pcixcap != 0)
2877 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
2893 struct bge_softc *sc;
2898 sc = device_get_softc(dev);
2899 sc->bge_dev = dev;
2901 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2909 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2912 if (sc->bge_res == NULL) {
2913 device_printf (sc->bge_dev, "couldn't map memory\n");
2919 sc->bge_chipid =
2922 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2932 sc->bge_chipid = pci_read_config(dev,
2941 sc->bge_chipid = pci_read_config(dev,
2945 sc->bge_chipid = pci_read_config(dev,
2949 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2950 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2968 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2969 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2970 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2972 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2973 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2979 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2991 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2992 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2993 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2994 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2995 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2996 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
2998 if (bge_has_eaddr(sc))
2999 sc->bge_flags |= BGE_FLAG_EADDR;
3002 switch (sc->bge_asicrev) {
3007 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3010 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3011 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3013 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3022 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3029 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3034 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3039 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3042 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3047 bge_add_sysctls(sc);
3050 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3051 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3052 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3053 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3054 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3055 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3056 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3057 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3059 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3060 if ((BGE_IS_5705_PLUS(sc)) &&
3061 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3062 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
3063 sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
3064 sc->bge_asicrev != BGE_ASICREV_BCM5720 &&
3065 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3066 sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
3067 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
3068 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3069 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3070 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3071 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3074 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3076 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3078 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3082 if (BGE_IS_5717_PLUS(sc) ||
3083 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3084 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3085 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3086 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3087 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3088 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3089 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3091 sc->bge_mi_mode = BGE_MIMODE_BASE;
3093 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3094 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3103 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3106 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3107 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3115 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3116 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3118 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3119 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3122 sc->bge_flags |= BGE_FLAG_5788;
3126 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3128 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3138 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3155 if (BGE_IS_5717_PLUS(sc)) {
3157 sc->bge_flags |= BGE_FLAG_TSO3;
3158 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3159 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3161 sc->bge_flags &= ~BGE_FLAG_TSO3;
3163 } else if (BGE_IS_5755_PLUS(sc)) {
3172 sc->bge_flags |= BGE_FLAG_TSO;
3183 sc->bge_flags |= BGE_FLAG_PCIE;
3184 sc->bge_expcap = reg;
3185 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3186 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3196 sc->bge_pcixcap = reg;
3199 sc->bge_flags |= BGE_FLAG_PCIX;
3207 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3208 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3217 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3218 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3225 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3226 sc->bge_msicap = reg;
3227 if (bge_can_use_msi(sc)) {
3235 sc->bge_flags |= BGE_FLAG_MSI;
3245 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3246 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3249 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3252 if (sc->bge_irq == NULL) {
3253 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3258 bge_devinfo(sc);
3260 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3263 if (bge_reset(sc)) {
3264 device_printf(sc->bge_dev, "chip reset failed\n");
3269 sc->bge_asf_mode = 0;
3270 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3272 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG)
3274 sc->bge_asf_mode |= ASF_ENABLE;
3275 sc->bge_asf_mode |= ASF_STACKUP;
3276 if (BGE_IS_575X_PLUS(sc))
3277 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3282 bge_stop_fw(sc);
3283 bge_sig_pre_reset(sc, BGE_RESET_STOP);
3284 if (bge_reset(sc)) {
3285 device_printf(sc->bge_dev, "chip reset failed\n");
3290 bge_sig_legacy(sc, BGE_RESET_STOP);
3291 bge_sig_post_reset(sc, BGE_RESET_STOP);
3293 if (bge_chipinit(sc)) {
3294 device_printf(sc->bge_dev, "chip initialization failed\n");
3299 error = bge_get_eaddr(sc, eaddr);
3301 device_printf(sc->bge_dev,
3308 if (BGE_IS_5717_PLUS(sc))
3309 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3310 else if (BGE_IS_5705_PLUS(sc))
3311 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3313 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3315 if (bge_dma_alloc(sc)) {
3316 device_printf(sc->bge_dev,
3323 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3324 sc->bge_rx_coal_ticks = 150;
3325 sc->bge_tx_coal_ticks = 150;
3326 sc->bge_rx_max_coal_bds = 10;
3327 sc->bge_tx_max_coal_bds = 10;
3330 sc->bge_csum_features = BGE_CSUM_FEATURES;
3331 if (sc->bge_forced_udpcsum != 0)
3332 sc->bge_csum_features |= CSUM_UDP;
3335 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3337 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3341 ifp->if_softc = sc;
3350 ifp->if_hwassist = sc->bge_csum_features;
3353 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3369 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3384 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3385 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3386 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3387 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3388 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3390 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3400 if (BGE_IS_5714_FAMILY(sc))
3401 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3403 sc->bge_flags |= BGE_FLAG_TBI;
3406 if (sc->bge_flags & BGE_FLAG_TBI) {
3407 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3409 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3410 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3412 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3413 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3414 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3424 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3426 bge_asf_driver_up(sc);
3428 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3433 device_printf(sc->bge_dev, "Try again\n");
3434 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
3438 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3445 if (sc->bge_asf_mode & ASF_STACKUP)
3446 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3457 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3458 sc->bge_flags & BGE_FLAG_PCIX)
3459 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3465 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3473 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3475 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3477 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3478 taskqueue_thread_enqueue, &sc->bge_tq);
3479 if (sc->bge_tq == NULL) {
3485 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3486 device_get_nameunit(sc->bge_dev));
3487 error = bus_setup_intr(dev, sc->bge_irq,
3488 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3489 &sc->bge_intrhand);
3493 error = bus_setup_intr(dev, sc->bge_irq,
3494 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3495 &sc->bge_intrhand);
3499 device_printf(sc->bge_dev, "couldn't set up irq\n");
3505 bge_release_resources(sc);
3513 struct bge_softc *sc;
3516 sc = device_get_softc(dev);
3517 ifp = sc->bge_ifp;
3524 BGE_LOCK(sc);
3525 bge_stop(sc);
3526 bge_reset(sc);
3527 BGE_UNLOCK(sc);
3529 callout_drain(&sc->bge_stat_ch);
3531 if (sc->bge_tq)
3532 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3535 if (sc->bge_flags & BGE_FLAG_TBI) {
3536 ifmedia_removeall(&sc->bge_ifmedia);
3539 device_delete_child(dev, sc->bge_miibus);
3542 bge_release_resources(sc);
3548 bge_release_resources(struct bge_softc *sc)
3552 dev = sc->bge_dev;
3554 if (sc->bge_tq != NULL)
3555 taskqueue_free(sc->bge_tq);
3557 if (sc->bge_intrhand != NULL)
3558 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3560 if (sc->bge_irq != NULL)
3562 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3564 if (sc->bge_flags & BGE_FLAG_MSI)
3567 if (sc->bge_res != NULL)
3569 PCIR_BAR(0), sc->bge_res);
3571 if (sc->bge_ifp != NULL)
3572 if_free(sc->bge_ifp);
3574 bge_dma_free(sc);
3576 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3577 BGE_LOCK_DESTROY(sc);
3581 bge_reset(struct bge_softc *sc)
3589 dev = sc->bge_dev;
3591 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3592 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3593 if (sc->bge_flags & BGE_FLAG_PCIE)
3610 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3611 BGE_IS_5755_PLUS(sc)) {
3614 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3622 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
3627 if (sc->bge_flags & BGE_FLAG_PCIE) {
3628 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
3629 CSR_WRITE_4(sc, 0x7E2C, 0x20);
3630 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3632 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3641 if (BGE_IS_5705_PLUS(sc) &&
3642 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
3646 write_op(sc, BGE_MISC_CFG, reset);
3648 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3649 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3650 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3652 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3653 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3660 if (sc->bge_flags & BGE_FLAG_PCIE) {
3661 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3667 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3671 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3674 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3686 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3692 if (sc->bge_flags & BGE_FLAG_PCIX) {
3694 sc->bge_pcixcap + PCIXR_COMMAND, 2);
3696 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3699 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3704 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3708 if (BGE_IS_5714_FAMILY(sc)) {
3710 if (sc->bge_flags & BGE_FLAG_MSI) {
3712 sc->bge_msicap + PCIR_MSI_CTRL, 2);
3714 sc->bge_msicap + PCIR_MSI_CTRL,
3716 val = CSR_READ_4(sc, BGE_MSI_MODE);
3717 CSR_WRITE_4(sc, BGE_MSI_MODE,
3720 val = CSR_READ_4(sc, BGE_MARB_MODE);
3721 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3723 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3725 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3727 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3745 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
3750 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3755 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
3774 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
3777 if (sc->bge_asf_mode & ASF_STACKUP)
3778 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3780 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3787 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3788 sc->bge_flags & BGE_FLAG_TBI) {
3789 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3791 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3795 if (sc->bge_flags & BGE_FLAG_PCIE &&
3796 !BGE_IS_5717_PLUS(sc) &&
3797 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3798 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3800 val = CSR_READ_4(sc, 0x7C00);
3801 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3805 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
3806 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
3813 bge_rxreuse_std(struct bge_softc *sc, int i)
3817 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3819 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3821 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3825 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3829 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3831 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3832 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3833 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3834 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3836 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3849 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3855 rx_cons = sc->bge_rx_saved_considx;
3861 ifp = sc->bge_ifp;
3863 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3864 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3865 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3866 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3867 if (BGE_IS_JUMBO_CAPABLE(sc) &&
3870 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3871 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3882 if (sc->rxcycles <= 0)
3884 sc->rxcycles--;
3888 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3891 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3901 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3903 bge_rxreuse_jumbo(sc, rxidx);
3906 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3907 bge_rxreuse_jumbo(sc, rxidx);
3911 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3914 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3916 bge_rxreuse_std(sc, rxidx);
3919 if (bge_newbuf_std(sc, rxidx) != 0) {
3920 bge_rxreuse_std(sc, rxidx);
3924 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3933 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3943 bge_rxcsum(sc, cur_rx, m);
3955 BGE_UNLOCK(sc);
3957 BGE_LOCK(sc);
3966 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3967 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3969 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3970 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3973 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3974 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3976 sc->bge_rx_saved_considx = rx_cons;
3977 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3979 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
3982 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
3989 if (BGE_IS_5705_PLUS(sc))
3990 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3996 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3999 if (BGE_IS_5717_PLUS(sc)) {
4031 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4036 BGE_LOCK_ASSERT(sc);
4039 if (sc->bge_tx_saved_considx == tx_cons)
4042 ifp = sc->bge_ifp;
4044 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4045 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4050 while (sc->bge_tx_saved_considx != tx_cons) {
4053 idx = sc->bge_tx_saved_considx;
4054 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4057 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4058 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4059 sc->bge_cdata.bge_tx_dmamap[idx],
4061 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4062 sc->bge_cdata.bge_tx_dmamap[idx]);
4063 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4064 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4066 sc->bge_txcnt--;
4067 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4071 if (sc->bge_txcnt == 0)
4072 sc->bge_timer = 0;
4079 struct bge_softc *sc = ifp->if_softc;
4084 BGE_LOCK(sc);
4086 BGE_UNLOCK(sc);
4090 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4091 sc->bge_cdata.bge_status_map,
4093 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4094 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4096 statusword = sc->bge_ldata.bge_status_block->bge_status;
4097 sc->bge_ldata.bge_status_block->bge_status = 0;
4099 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4100 sc->bge_cdata.bge_status_map,
4105 sc->bge_link_evt++;
4108 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4109 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4110 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4111 bge_link_upd(sc);
4113 sc->rxcycles = count;
4114 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4116 BGE_UNLOCK(sc);
4119 bge_txeof(sc, tx_cons);
4123 BGE_UNLOCK(sc);
4131 struct bge_softc *sc;
4133 sc = (struct bge_softc *)arg;
4138 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4145 struct bge_softc *sc;
4150 sc = (struct bge_softc *)arg;
4151 ifp = sc->bge_ifp;
4153 BGE_LOCK(sc);
4155 BGE_UNLOCK(sc);
4160 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4161 sc->bge_cdata.bge_status_map,
4165 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4166 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4167 status = sc->bge_ldata.bge_status_block->bge_status;
4168 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4169 sc->bge_ldata.bge_status_block->bge_status = 0;
4170 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4171 sc->bge_cdata.bge_status_map,
4173 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4177 bge_link_upd(sc);
4180 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4183 sc->bge_rx_saved_considx != rx_prod) {
4185 BGE_UNLOCK(sc);
4186 bge_rxeof(sc, rx_prod, 0);
4187 BGE_LOCK(sc);
4191 bge_txeof(sc, tx_cons);
4195 BGE_UNLOCK(sc);
4201 struct bge_softc *sc;
4206 sc = xsc;
4208 BGE_LOCK(sc);
4210 ifp = sc->bge_ifp;
4214 BGE_UNLOCK(sc);
4239 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4244 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4247 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4248 sc->bge_cdata.bge_status_map,
4250 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4251 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4252 sc->bge_ldata.bge_status_block->bge_status = 0;
4253 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4254 sc->bge_cdata.bge_status_map,
4257 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4258 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4259 statusword || sc->bge_link_evt)
4260 bge_link_upd(sc);
4264 bge_rxeof(sc, rx_prod, 1);
4269 bge_txeof(sc, tx_cons);
4276 BGE_UNLOCK(sc);
4280 bge_asf_driver_up(struct bge_softc *sc)
4282 if (sc->bge_asf_mode & ASF_STACKUP) {
4284 if (sc->bge_asf_count)
4285 sc->bge_asf_count --;
4287 sc->bge_asf_count = 2;
4288 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4290 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4291 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4293 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4294 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4303 struct bge_softc *sc = xsc;
4306 BGE_LOCK_ASSERT(sc);
4309 if (callout_pending(&sc->bge_stat_ch) ||
4310 !callout_active(&sc->bge_stat_ch))
4313 if (BGE_IS_5705_PLUS(sc))
4314 bge_stats_update_regs(sc);
4316 bge_stats_update(sc);
4318 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4319 mii = device_get_softc(sc->bge_miibus);
4325 if (!sc->bge_link)
4335 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4338 sc->bge_link_evt++;
4339 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4340 sc->bge_flags & BGE_FLAG_5788)
4341 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4343 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4347 bge_asf_driver_up(sc);
4348 bge_watchdog(sc);
4350 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4354 bge_stats_update_regs(struct bge_softc *sc)
4359 ifp = sc->bge_ifp;
4360 stats = &sc->bge_mac_stats;
4363 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4365 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4367 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4369 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4371 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4373 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4375 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4377 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4379 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4381 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4383 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4385 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4387 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4390 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4392 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4394 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4396 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4398 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4400 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4402 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4404 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4406 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4408 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4410 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4412 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4414 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4416 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4419 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4421 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4423 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4425 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4445 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4446 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4447 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4449 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4451 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4453 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4461 bge_stats_clear_regs(struct bge_softc *sc)
4464 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4465 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4466 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4467 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4468 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4469 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4470 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4471 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4472 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4473 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4474 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4475 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4476 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4478 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4479 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4480 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4481 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4482 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4483 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4484 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4485 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4486 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4487 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4488 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4489 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4490 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4491 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4493 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4494 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4495 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4496 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4497 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4498 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4499 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4503 bge_stats_update(struct bge_softc *sc)
4509 ifp = sc->bge_ifp;
4513 #define READ_STAT(sc, stats, stat) \
4514 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4516 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4517 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4518 sc->bge_tx_collisions = cnt;
4520 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4521 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
4522 sc->bge_rx_nobds = cnt;
4523 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4524 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
4525 sc->bge_rx_inerrs = cnt;
4526 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4527 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4528 sc->bge_rx_discards = cnt;
4530 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4531 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4532 sc->bge_tx_discards = cnt;
4616 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4664 if (sc->bge_flags & BGE_FLAG_TSO3) {
4692 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
4705 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4713 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4718 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4737 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4740 if (sc->bge_forced_collapse > 0 &&
4741 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4747 if (sc->bge_forced_collapse == 1)
4751 sc->bge_forced_collapse);
4758 map = sc->bge_cdata.bge_tx_dmamap[idx];
4759 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4769 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4780 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4781 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4785 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4792 d = &sc->bge_ldata.bge_tx_ring[idx];
4812 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4813 sc->bge_cdata.bge_tx_dmamap[idx] = map;
4814 sc->bge_cdata.bge_tx_chain[idx] = m;
4815 sc->bge_txcnt += nsegs;
4830 struct bge_softc *sc;
4835 sc = ifp->if_softc;
4836 BGE_LOCK_ASSERT(sc);
4838 if (!sc->bge_link ||
4843 prodidx = sc->bge_tx_prodidx;
4846 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4869 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4882 if (bge_encap(sc, &m_head, &prodidx)) {
4903 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4904 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4906 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4908 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4909 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4911 sc->bge_tx_prodidx = prodidx;
4916 sc->bge_timer = 5;
4927 struct bge_softc *sc;
4929 sc = ifp->if_softc;
4930 BGE_LOCK(sc);
4932 BGE_UNLOCK(sc);
4936 bge_init_locked(struct bge_softc *sc)
4942 BGE_LOCK_ASSERT(sc);
4944 ifp = sc->bge_ifp;
4950 bge_stop(sc);
4952 bge_stop_fw(sc);
4953 bge_sig_pre_reset(sc, BGE_RESET_START);
4954 bge_reset(sc);
4955 bge_sig_legacy(sc, BGE_RESET_START);
4956 bge_sig_post_reset(sc, BGE_RESET_START);
4958 bge_chipinit(sc);
4964 if (bge_blockinit(sc)) {
4965 device_printf(sc->bge_dev, "initialization failure\n");
4969 ifp = sc->bge_ifp;
4972 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4977 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4978 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4979 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4982 bge_setpromisc(sc);
4985 bge_setmulti(sc);
4988 bge_setvlan(sc);
4991 if (sc->bge_forced_udpcsum == 0)
4992 sc->bge_csum_features &= ~CSUM_UDP;
4994 sc->bge_csum_features |= CSUM_UDP;
4998 ifp->if_hwassist |= sc->bge_csum_features;
5002 if (bge_init_rx_ring_std(sc) != 0) {
5003 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5004 bge_stop(sc);
5013 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5017 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5022 device_printf (sc->bge_dev,
5027 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5030 if (bge_init_rx_ring_jumbo(sc) != 0) {
5031 device_printf(sc->bge_dev,
5033 bge_stop(sc);
5039 sc->bge_rx_saved_considx = 0;
5042 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5045 bge_init_tx_ring(sc);
5048 mode = CSR_READ_4(sc, BGE_TX_MODE);
5049 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5051 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
5053 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5057 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5060 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5068 if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
5069 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5071 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5074 if (BGE_IS_5705_PLUS(sc))
5075 bge_stats_clear_regs(sc);
5078 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5083 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5085 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5091 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5092 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5093 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5101 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5107 struct bge_softc *sc = xsc;
5109 BGE_LOCK(sc);
5110 bge_init_locked(sc);
5111 BGE_UNLOCK(sc);
5120 struct bge_softc *sc = ifp->if_softc;
5123 BGE_LOCK(sc);
5125 BGE_UNLOCK(sc);
5133 struct bge_softc *sc = ifp->if_softc;
5138 BGE_LOCK_ASSERT(sc);
5140 ifm = &sc->bge_ifmedia;
5143 if (sc->bge_flags & BGE_FLAG_TBI) {
5153 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5155 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5157 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5158 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5162 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5165 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5171 BGE_CLRBIT(sc, BGE_MAC_MODE,
5174 BGE_SETBIT(sc, BGE_MAC_MODE,
5184 sc->bge_link_evt++;
5185 mii = device_get_softc(sc->bge_miibus);
5202 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5203 sc->bge_flags & BGE_FLAG_5788)
5204 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5206 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5217 struct bge_softc *sc = ifp->if_softc;
5220 BGE_LOCK(sc);
5222 if (sc->bge_flags & BGE_FLAG_TBI) {
5225 if (CSR_READ_4(sc, BGE_MAC_STS) &
5230 BGE_UNLOCK(sc);
5234 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5238 BGE_UNLOCK(sc);
5242 mii = device_get_softc(sc->bge_miibus);
5247 BGE_UNLOCK(sc);
5253 struct bge_softc *sc = ifp->if_softc;
5260 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5261 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5271 BGE_LOCK(sc);
5276 bge_init_locked(sc);
5279 BGE_UNLOCK(sc);
5282 BGE_LOCK(sc);
5293 flags = ifp->if_flags ^ sc->bge_if_flags;
5295 bge_setpromisc(sc);
5297 bge_setmulti(sc);
5299 bge_init_locked(sc);
5302 bge_stop(sc);
5305 sc->bge_if_flags = ifp->if_flags;
5306 BGE_UNLOCK(sc);
5312 BGE_LOCK(sc);
5313 bge_setmulti(sc);
5314 BGE_UNLOCK(sc);
5320 if (sc->bge_flags & BGE_FLAG_TBI) {
5322 &sc->bge_ifmedia, command);
5324 mii = device_get_softc(sc->bge_miibus);
5337 BGE_LOCK(sc);
5338 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5340 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5342 BGE_UNLOCK(sc);
5346 BGE_LOCK(sc);
5347 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5349 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5351 BGE_UNLOCK(sc);
5359 ifp->if_hwassist |= sc->bge_csum_features;
5361 ifp->if_hwassist &= ~sc->bge_csum_features;
5380 bge_init(sc);
5391 BGE_LOCK(sc);
5392 bge_setvlan(sc);
5393 BGE_UNLOCK(sc);
5408 bge_watchdog(struct bge_softc *sc)
5412 BGE_LOCK_ASSERT(sc);
5414 if (sc->bge_timer == 0 || --sc->bge_timer)
5417 ifp = sc->bge_ifp;
5422 bge_init_locked(sc);
5428 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5432 BGE_CLRBIT(sc, reg, bit);
5435 if ((CSR_READ_4(sc, reg) & bit) == 0)
5446 bge_stop(struct bge_softc *sc)
5450 BGE_LOCK_ASSERT(sc);
5452 ifp = sc->bge_ifp;
5454 callout_stop(&sc->bge_stat_ch);
5457 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5458 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5463 bge_stop_fw(sc);
5464 bge_sig_pre_reset(sc, BGE_RESET_STOP);
5469 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5470 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5471 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5472 if (BGE_IS_5700_FAMILY(sc))
5473 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5474 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5475 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5476 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5481 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5482 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5483 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5484 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5485 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5486 if (BGE_IS_5700_FAMILY(sc))
5487 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5488 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5494 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5495 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5496 if (BGE_IS_5700_FAMILY(sc))
5497 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5499 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5500 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5501 if (!(BGE_IS_5705_PLUS(sc))) {
5502 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5503 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5506 if (BGE_IS_5705_PLUS(sc))
5507 bge_stats_update_regs(sc);
5509 bge_reset(sc);
5510 bge_sig_legacy(sc, BGE_RESET_STOP);
5511 bge_sig_post_reset(sc, BGE_RESET_STOP);
5516 if (sc->bge_asf_mode & ASF_STACKUP)
5517 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5519 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5522 bge_free_rx_ring_std(sc);
5525 if (BGE_IS_JUMBO_CAPABLE(sc))
5526 bge_free_rx_ring_jumbo(sc);
5529 bge_free_tx_ring(sc);
5531 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5534 if (bootverbose && sc->bge_link)
5535 if_printf(sc->bge_ifp, "link DOWN\n");
5536 sc->bge_link = 0;
5548 struct bge_softc *sc;
5550 sc = device_get_softc(dev);
5551 BGE_LOCK(sc);
5552 bge_stop(sc);
5553 bge_reset(sc);
5554 BGE_UNLOCK(sc);
5562 struct bge_softc *sc;
5564 sc = device_get_softc(dev);
5565 BGE_LOCK(sc);
5566 bge_stop(sc);
5567 BGE_UNLOCK(sc);
5575 struct bge_softc *sc;
5578 sc = device_get_softc(dev);
5579 BGE_LOCK(sc);
5580 ifp = sc->bge_ifp;
5582 bge_init_locked(sc);
5586 BGE_UNLOCK(sc);
5592 bge_link_upd(struct bge_softc *sc)
5597 BGE_LOCK_ASSERT(sc);
5600 sc->bge_link_evt = 0;
5617 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5618 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5619 status = CSR_READ_4(sc, BGE_MAC_STS);
5621 mii = device_get_softc(sc->bge_miibus);
5623 if (!sc->bge_link &&
5626 sc->bge_link++;
5628 if_printf(sc->bge_ifp, "link UP\n");
5629 } else if (sc->bge_link &&
5632 sc->bge_link = 0;
5634 if_printf(sc->bge_ifp, "link DOWN\n");
5638 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5640 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
5641 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
5647 if (sc->bge_flags & BGE_FLAG_TBI) {
5648 status = CSR_READ_4(sc, BGE_MAC_STS);
5650 if (!sc->bge_link) {
5651 sc->bge_link++;
5652 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
5653 BGE_CLRBIT(sc, BGE_MAC_MODE,
5655 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5657 if_printf(sc->bge_ifp, "link UP\n");
5658 if_link_state_change(sc->bge_ifp,
5661 } else if (sc->bge_link) {
5662 sc->bge_link = 0;
5664 if_printf(sc->bge_ifp, "link DOWN\n");
5665 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
5667 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
5673 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
5675 if (link != sc->bge_link ||
5676 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
5677 mii = device_get_softc(sc->bge_miibus);
5679 if (!sc->bge_link &&
5682 sc->bge_link++;
5684 if_printf(sc->bge_ifp, "link UP\n");
5685 } else if (sc->bge_link &&
5688 sc->bge_link = 0;
5690 if_printf(sc->bge_ifp, "link DOWN\n");
5698 mii = device_get_softc(sc->bge_miibus);
5700 bge_miibus_statchg(sc->bge_dev);
5704 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
5710 bge_add_sysctls(struct bge_softc *sc)
5717 ctx = device_get_sysctl_ctx(sc->bge_dev);
5718 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
5722 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
5726 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
5730 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
5735 unit = device_get_unit(sc->bge_dev);
5748 sc->bge_forced_collapse = 0;
5750 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
5752 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
5756 sc->bge_msi = 1;
5758 TUNABLE_INT_FETCH(tn, &sc->bge_msi);
5760 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
5772 sc->bge_forced_udpcsum = 0;
5774 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
5776 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
5780 if (BGE_IS_5705_PLUS(sc))
5781 bge_add_sysctl_stats_regs(sc, ctx, children);
5783 bge_add_sysctl_stats(sc, ctx, children);
5786 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
5788 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
5792 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5801 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
5804 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
5806 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
5808 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
5810 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
5812 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
5814 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
5816 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
5818 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
5820 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
5822 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
5824 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
5826 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
5828 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
5830 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
5836 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5838 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5840 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5842 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5844 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5846 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5848 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5850 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5853 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5856 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5858 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5860 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5862 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5864 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5866 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5872 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5874 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5876 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5878 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5880 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5882 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5885 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5888 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5891 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5894 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5897 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5900 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5902 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5904 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5906 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5909 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5911 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5921 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5928 stats = &sc->bge_mac_stats;
6018 struct bge_softc *sc;
6022 sc = (struct bge_softc *)arg1;
6024 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6033 struct bge_softc *sc;
6044 sc = (struct bge_softc *)arg1;
6046 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6047 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6051 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6053 BGE_LOCK(sc);
6054 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6055 sc->bge_cdata.bge_status_map,
6068 printf(" %08x", CSR_READ_4(sc, i));
6073 BGE_UNLOCK(sc);
6076 if (BGE_IS_5717_PLUS(sc))
6078 if (BGE_IS_5755_PLUS(sc))
6080 if (BGE_IS_575X_PLUS(sc))
6082 if (BGE_IS_5705_PLUS(sc))
6084 if (BGE_IS_5714_FAMILY(sc))
6086 if (BGE_IS_5700_FAMILY(sc))
6088 if (sc->bge_flags & BGE_FLAG_JUMBO)
6090 if (sc->bge_flags & BGE_FLAG_PCIX)
6092 if (sc->bge_flags & BGE_FLAG_PCIE)
6094 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6096 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6106 struct bge_softc *sc;
6117 sc = (struct bge_softc *)arg1;
6118 val = CSR_READ_4(sc, result);
6128 struct bge_softc *sc;
6139 sc = (struct bge_softc *)arg1;
6140 val = bge_readmem_ind(sc, result);
6149 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6152 if (sc->bge_flags & BGE_FLAG_EADDR)
6156 OF_getetheraddr(sc->bge_dev, ether_addr);
6163 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6167 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6171 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6182 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6186 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6189 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6194 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6197 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6200 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6205 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6218 if ((*func)(sc, eaddr) == 0)