Lines Matching defs:disp_setting
16 zx_status_t AmlDsiHost::HostModeInit(uint32_t opp, const DisplaySetting& disp_setting) {
17 uint32_t lane_num = disp_setting.lane_num;
52 WRITE32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE, disp_setting.h_active);
58 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HLINE_TIME, disp_setting.h_period);
59 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HSA_TIME, disp_setting.hsync_width);
60 WRITE32_REG(MIPI_DSI, DW_DSI_VID_HBP_TIME, disp_setting.hsync_bp);
61 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VSA_LINES, disp_setting.vsync_width);
62 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VBP_LINES, disp_setting.vsync_bp);
63 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VACTIVE_LINES, disp_setting.v_active);
64 WRITE32_REG(MIPI_DSI, DW_DSI_VID_VFP_LINES, (disp_setting.v_period -
65 disp_setting.v_active - disp_setting.vsync_bp -
66 disp_setting.vsync_width));
105 void AmlDsiHost::HostOff(const DisplaySetting& disp_setting) {
113 HostModeInit(COMMAND_MODE, disp_setting);
127 zx_status_t AmlDsiHost::HostOn(const DisplaySetting& disp_setting) {
144 zx_status_t status = phy_->Init(parent_, disp_setting.lane_num);
176 if ((status = HostModeInit(COMMAND_MODE, disp_setting)) != ZX_OK) {
210 if ((status = HostModeInit(VIDEO_MODE, disp_setting)) != ZX_OK) {