dev/pcie/pcie_irqs.cpp

38     if (irq_.handler_count > 1) {
39         DEBUG_ASSERT(irq_.handlers != &irq_.singleton_handler);
40         delete[] irq_.handlers;
43     irq_.singleton_handler.handler = nullptr;
44     irq_.singleton_handler.ctx = nullptr;
45     irq_.singleton_handler.dev = nullptr;
46     irq_.mode          = PCIE_IRQ_MODE_DISABLED;
47     irq_.handlers      = nullptr;
48     irq_.handler_count = 0;
53     DEBUG_ASSERT(!irq_.handlers);
54     DEBUG_ASSERT(!irq_.handler_count);
57         irq_.handlers      = &irq_.singleton_handler;
58         irq_.handler_count = 1;
61         irq_.handlers = new (&ac) pcie_irq_handler_state_t[requested_irqs];
66         irq_.handler_count = requested_irqs;
69     for (uint i = 0; i < irq_.handler_count; ++i) {
70         DEBUG_ASSERT(irq_.handlers[i].handler == nullptr);
71         DEBUG_ASSERT(irq_.handlers[i].dev == nullptr);
72         DEBUG_ASSERT(irq_.handlers[i].ctx == nullptr);
73         irq_.handlers[i].dev        = this;
74         irq_.handlers[i].pci_irq_id = i;
75         irq_.handlers[i].masked     = is_masked;
133                          irq_.legacy.shared_handler_node) {
145             pcie_irq_handler_state_t* hstate  = &dev->irq_.handlers[0];
155                     TRACEF("Received legacy PCI INT (system IRQ %u) for %02x:%02x.%02x, but no irq_ "
170                 TRACEF("Received legacy PCI INT (system IRQ %u) for %02x:%02x.%02x , but no irq_ "
185     DEBUG_ASSERT(dev.irq_.legacy.shared_handler.get() == this);
186     DEBUG_ASSERT(!list_in_list(&dev.irq_.legacy.shared_handler_node));
198     list_add_tail(&device_handler_list_, &dev.irq_.legacy.shared_handler_node);
205     DEBUG_ASSERT(dev.irq_.legacy.shared_handler.get() == this);
206     DEBUG_ASSERT(list_in_list(&dev.irq_.legacy.shared_handler_node));
215     list_delete(&dev.irq_.legacy.shared_handler_node);
222     if (!irq_.handlers || !irq_.handler_count)
225     pcie_irq_handler_state_t& hstate = irq_.handlers[0];
241     if (!irq_.legacy.pin || (requested_irqs > 1))
251     DEBUG_ASSERT(irq_.handlers == &irq_.singleton_handler);
253     irq_.mode = PCIE_IRQ_MODE_LEGACY;
254     irq_.legacy.shared_handler->AddDevice(*this);
262     irq_.legacy.shared_handler->RemoveDevice(*this);
274     DEBUG_ASSERT(irq_.mode == PCIE_IRQ_MODE_MSI);
275     DEBUG_ASSERT(irq_id < irq_.handler_count);
276     DEBUG_ASSERT(irq_.handlers);
278     pcie_irq_handler_state_t& hstate = irq_.handlers[irq_id];
285                  irq_.msi->has_pvm());
288     if (irq_.msi->has_pvm()) {
290         uint32_t  val  = cfg_->Read(irq_.msi->mask_bits_reg());
293         cfg_->Write(irq_.msi->mask_bits_reg(), val);
297     DEBUG_ASSERT(irq_.msi->irq_block_.allocated);
298     DEBUG_ASSERT(irq_id < irq_.msi->irq_block_.num_irq);
300         bus_drv_.platform().MaskUnmaskMsi(&irq_.msi->irq_block_, irq_id, mask);
308     if (irq_id >= irq_.handler_count)
314     if (mask && !bus_drv_.platform().supports_msi_masking() && !irq_.msi->has_pvm())
317     DEBUG_ASSERT(irq_.handlers);
320         AutoSpinLock handler_lock(&irq_.handlers[irq_id].lock);
328     DEBUG_ASSERT(irq_.msi);
329     DEBUG_ASSERT(irq_.msi->is_valid());
331     for (uint i = 0; i < irq_.handler_count; i++)
337     if (irq_.msi->has_pvm())
338         cfg_->Write(irq_.msi->mask_bits_reg(), 0xFFFFFFFF);
342     DEBUG_ASSERT(irq_.msi);
343     DEBUG_ASSERT(irq_.msi->is_valid());
344     DEBUG_ASSERT(irq_.msi->is64Bit() || !(tgt_addr >> 32));
355     cfg_->Write(irq_.msi->addr_reg(), static_cast<uint32_t>(tgt_addr & 0xFFFFFFFF));
356     if (irq_.msi->is64Bit()) {
357         cfg_->Write(irq_.msi->addr_upper_reg(), static_cast<uint32_t>(tgt_addr >> 32));
359     cfg_->Write(irq_.msi->data_reg(), static_cast<uint16_t>(tgt_data & 0xFFFF));
364     if (!irq_.msi->irq_block_.allocated)
371     const msi_block_t* b = &irq_.msi->irq_block_;
380     bus_drv_.platform().FreeMsiBlock(&irq_.msi->irq_block_);
381     DEBUG_ASSERT(!irq_.msi->irq_block_.allocated);
385     DEBUG_ASSERT(irq_.msi);
386     DEBUG_ASSERT(irq_.msi->is_valid());
395     cfg_->Write(irq_.msi->ctrl_reg(),
396             PCIE_CAP_MSI_CTRL_SET_MME(log2, cfg_->Read(irq_.msi->ctrl_reg())));
403     /* Return any allocated irq_ block to the platform, unregistering with
419     if (!irq_.msi                             ||
420         !irq_.msi->is_valid()                 ||
422         (requested_irqs > irq_.msi->max_irqs()))
428     if (irq_.msi->has_pvm()) {
429         cfg_->Write(irq_.msi->mask_bits_reg(), 0xFFFFFFFF);
439     DEBUG_ASSERT(!irq_.msi->irq_block_.allocated);
441                                             irq_.msi->is64Bit(),
443                                             &irq_.msi->irq_block_);
457     irq_.mode = PCIE_IRQ_MODE_MSI;
466     DEBUG_ASSERT(irq_.msi->irq_block_.allocated);
467     SetMsiTarget(irq_.msi->irq_block_.tgt_addr, irq_.msi->irq_block_.tgt_data);
473     DEBUG_ASSERT(irq_.handler_count <= irq_.msi->irq_block_.num_irq);
474     for (uint i = 0; i < irq_.handler_count; ++i) {
475         bus_drv_.platform().RegisterMsiHandler(&irq_.msi->irq_block_,
478                                                irq_.handlers + i);
492     DEBUG_ASSERT(irq_.msi);
498     if (bus_drv_.platform().supports_msi_masking() || irq_.msi->has_pvm()) {
546         if (!irq_.legacy.pin)
561         if (!irq_.msi || !irq_.msi->is_valid())
567         out_caps->max_irqs = irq_.msi->max_irqs();
568         out_caps->per_vector_masking_supported = irq_.msi->has_pvm()
593     out_info->mode                = irq_.mode;
594     out_info->max_handlers        = irq_.handler_count;
595     out_info->registered_handlers = irq_.registered_handler_count;
616     switch (irq_.mode) {
618         DEBUG_ASSERT(list_in_list(&irq_.legacy.shared_handler_node));
623         DEBUG_ASSERT(irq_.msi);
624         DEBUG_ASSERT(irq_.msi->is_valid());
625         DEBUG_ASSERT(irq_.msi->irq_block_.allocated);
636         DEBUG_ASSERT(!irq_.handlers);
637         DEBUG_ASSERT(!irq_.handler_count);
658     if (irq_.mode == PCIE_IRQ_MODE_DISABLED)
661     DEBUG_ASSERT(irq_.handlers);
662     DEBUG_ASSERT(irq_.handler_count);
665     if (irq_id >= irq_.handler_count)
669     pcie_irq_handler_state_t& hstate = irq_.handlers[irq_id];
673         DEBUG_ASSERT(irq_.registered_handler_count);
675             irq_.registered_handler_count--;
678             irq_.registered_handler_count++;
680     DEBUG_ASSERT(irq_.registered_handler_count <= irq_.handler_count);
696     if (irq_.mode == PCIE_IRQ_MODE_DISABLED)
699     DEBUG_ASSERT(irq_.handlers);
700     DEBUG_ASSERT(irq_.handler_count);
703     if (irq_id >= irq_.handler_count)
708     pcie_irq_handler_state_t& hstate = irq_.handlers[irq_id];
714     switch (irq_.mode) {
869                bus_id_, dev_id_, func_id_, irq_.legacy.pin,
879     return root->Swizzle(dev->dev_id(), dev->func_id(), pin, &irq_.legacy.irq_id);
885     DEBUG_ASSERT(irq_.legacy.shared_handler == nullptr);
893     irq_.legacy.pin = cfg_->Read(PciConfig::kInterruptPin);
894     if (irq_.legacy.pin) {
900                    irq_.legacy.pin);
904         irq_.legacy.shared_handler = bus_drv_.FindLegacyIrqHandler(irq_.legacy.irq_id);
905         if (irq_.legacy.shared_handler == nullptr) {
909                    irq_.legacy.pin, irq_.legacy.irq_id);