arch/arm64/mmu.cpp

188 static void s1_pte_attr_to_mmu_flags(pte_t pte, uint* mmu_flags) {
189     switch (pte & MMU_PTE_ATTR_ATTR_INDEX_MASK) {
207     switch (pte & MMU_PTE_ATTR_AP_MASK) {
221     if (!((pte & MMU_PTE_ATTR_UXN) && (pte & MMU_PTE_ATTR_PXN))) {
224     if (pte & MMU_PTE_ATTR_NON_SECURE) {
261 static void s2_pte_attr_to_mmu_flags(pte_t pte, uint* mmu_flags) {
262     switch (pte & MMU_S2_PTE_ATTR_ATTR_INDEX_MASK) {
280     switch (pte & MMU_PTE_ATTR_AP_MASK) {
290     if (pte & MMU_S2_PTE_ATTR_XN) {
304     pte_t pte;
350         pte = page_table[index];
351         descriptor_type = pte & MMU_PTE_DESCRIPTOR_MASK;
352         pte_addr = pte & MMU_PTE_OUTPUT_ADDR_MASK;
355                 ", pte %#" PRIx64 "\n",
356                 vaddr, index, index_shift, vaddr_rem, pte);
379             s2_pte_attr_to_mmu_flags(pte, mmu_flags);
381             s1_pte_attr_to_mmu_flags(pte, mmu_flags);
431     pte_t pte;
437     pte = page_table[index];
438     switch (pte & MMU_PTE_DESCRIPTOR_MASK) {
453         pte = paddr | MMU_PTE_L012_DESCRIPTOR_TABLE;
454         page_table[index] = pte;
455         LTRACEF("pte %p[%#" PRIxPTR "] = %#" PRIx64 "\n",
456                 page_table, index, pte);
460         paddr = pte & MMU_PTE_OUTPUT_ADDR_MASK;
475     pte_t pte;
478         pte = page_table[i];
479         if (pte != MMU_PTE_DESCRIPTOR_INVALID) {
481                     page_table, i, pte);
525     pte_t pte;
540         pte = page_table[index];
543             (pte & MMU_PTE_DESCRIPTOR_MASK) == MMU_PTE_L012_DESCRIPTOR_TABLE) {
544             page_table_paddr = pte & MMU_PTE_OUTPUT_ADDR_MASK;
551                 LTRACEF("pte %p[0x%lx] = 0 (was page table)\n", page_table, index);
563         } else if (pte) {
564             LTRACEF("pte %p[0x%lx] = 0\n", page_table, index);
573             LTRACEF("pte %p[0x%lx] already clear\n", page_table, index);
601     pte_t pte;
636             pte = page_table[index];
637             if (pte) {
639                        index, pte);
643             pte = paddr | attrs;
645                 pte |= MMU_PTE_L012_DESCRIPTOR_BLOCK;
647                 pte |= MMU_PTE_L3_DESCRIPTOR_PAGE;
649                 pte |= MMU_PTE_ATTR_NON_GLOBAL;
650             LTRACEF("pte %p[%#" PRIxPTR "] = %#" PRIx64 "\n",
651                     page_table, index, pte);
652             page_table[index] = pte;
685     pte_t pte;
704         pte = page_table[index];
707             (pte & MMU_PTE_DESCRIPTOR_MASK) == MMU_PTE_L012_DESCRIPTOR_TABLE) {
708             page_table_paddr = pte & MMU_PTE_OUTPUT_ADDR_MASK;
716         } else if (pte) {
717             pte = (pte & ~MMU_PTE_PERMISSION_MASK) | attrs;
718             LTRACEF("pte %p[%#" PRIxPTR "] = %#" PRIx64 "\n",
719                     page_table, index, pte);
720             page_table[index] = pte;
730                     index, pte);